ScienceDirect Alert: Solid-State Electronics, Vol. 62, Iss. 1, 2011

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Solid-State Electronics Volume 62, Issue 1,  Pages 1-202 (August 2011) Modify or Remove My Alerts

1.

Editorial Board    Page IFC

Letter

2.

Tunneling coefficient for GaN Schottky barrier diodes    Pages 1-4 A. Merve Ozbek, B. Jayant Baliga

Regular Papers

3.

Atomistic and electrical simulations of a GaN–AlN–(4H)SiC heterostructure optically-triggered vertical power semiconductor device   Original Research Article Pages 5-13 Srikanta Bose, Sudip K. Mazumder Highlights ► Molecular dynamics simulation is conducted for the GaN–AlN–(4H)SiC heteroepitaxial system. ► The density of states at the Fermi-level for 1 nm of AlN as the interface material is observed. ► The above favors to the possibility of vertical electrical conduction across the heterostructure. ► To verify the atomistic study, an electrical simulation is carried out for a vertical NPN device. ► GaN/(4H)SiC vertical NPN device shows better switching characteristics over all-(4H)SiC device.

4.

Efficiency improvement of polymer light-emitting devices using titanium and titanium dioxide as electron injecting layers   Original Research Article Pages 14-18 Mariya Aleksandrova, Milka Rassovska, Georgy Dobrikov Highlights ► In this study we examined titanium and titanium dioxide as electron injecting layers in polymer light-emitting devices. ► We established efficiency improvement in comparison with the device without electron injecting layer. ► We concluded that the performance of the device with a Ti/Al cathode is less sensitive to the injection layer thickness. ► We found that these bilayer cathodes are very effective to be used together with different electroluminescent polymers. ► We ascribed the good performance to the suitable energy level alignment and low contact resistance.

5.

Impact of drain bias stress on forward/reverse mode operation of amorphous ZIO TFTs   Original Research Article Pages 19-24 Aritra Dey, David R. Allee, Lawrence T. Clark Highlights ► This paper studies the impact of drain bias stress, under fixed gate bias in a-IZO TFTs. ► The change in VT is more for higher drain bias. ► Both subthreshold slope and transfer characteristics change but recover when left unstressed. ► The degradation follows logarithmic model, associated with charge trapping. ► All observations point to charge trapping as degradation mechanism.

6.

Electrical properties of metal–ferroelectric–insulator–semiconductor structure using BaxSr1−xTiO3 for ferroelectric–gate field effect transistor   Original Research Article Pages 25-30 Ala’eddin A. Saif, P. Poopalan Highlights ► The memory window width increases with the increase both of Ba content and film thickness. ► The memory window increases as the applied voltage increases. ► The low value of the leakage current indicates the good insulating characteristics of the films.

7.

A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates   Original Research Article Pages 31-39 Darsen D. Lu, Mohan V. Dunga, Chung-Hsun Lin, Ali M. Niknejad, Chenming Hu Research highlights ► A computationally efficient approximation for surface potential in FDSOI MOSFETs is developed. ► I–V and C–V models for FDSOI MOSFETs are derived without making the charge sheet approximation. ► The core model and non-ideal effect expressions are implemented in Verilog-A language. ► The model is symmetric with respect to Vds = 0 and continuous in all regions of operation.

8.

Bipolar resistive switching of chromium oxide for resistive random access memory   Original Research Article Pages 40-43 Shih-Cheng Chen, Ting-Chang Chang, Shih-Yang Chen, Chi-Wen Chen, Shih-Ching Chen, S.M. Sze, Ming-Jinn Tsai, Ming-Jer Kao, Fon-Shan Yeh Research highlights ► This study investigates the resistance switching characteristics of Cr2O3-based resistance random access memory (RRAM) with Pt/Cr2O3/TiN and Pt/Cr2O3/Pt structures. Only devices with Pt/Cr2O3/TiN structure exhibit bipolar switching behavior after the forming process because TiN was able to work as an effective oxygen reservoir but Pt was not. Oxygen migration between Cr2O3 and TiN was observed clearly before and after resistance switching from Auger electron spectroscopy (AES) analysis. Both low resistance state, ON state, and high resistance state, OFF state, of Pt/Cr2O3/TiN structures are stable and reproducible during a successive resistive switching. The resistance ratio of ON and OFF state is over 102, on top of that, the retention properties of both states are very stable after 104 seconds with a voltage of −0.2V.

9.

Structural and electrical characteristics of RF-sputtered HfO2 high-k based MOS capacitors   Original Research Article Pages 44-47 P.M. Tirmali, Anil G. Khairnar, Bhavana N. Joshi, A.M. Mahajan Research highlights ► In this study we have deposited and analyzed the HfO2 as the high-k dielectric for MOS capacitor. ► The AFM studies prove the deposited films are very much smooth and this smoothness improves on annealing. ► It is observed that flat-band voltage (VFB) shifts towards negative potential due to positive trap charge. ► The annealed HfO2 films show very low leakage current of 9.12 × 10−6 A/cm2 at 1V.

10.

An effective thermal circuit model for electro-thermal simulation of SOI analog circuits   Original Research Article Pages 48-61 Ming-C. Cheng, Kun Zhang Highlights ► A thermal circuit model is developed for SOI analog circuits. ► The model integrates a device thermal circuit with interconnect thermal networks. ► The device thermal circuit accounts for non-isothermal effects in SOI devices. ► Thermal networks for cross-coupled and parallel coupled wires are developed. ► The model is coupled with BSIMSOI for electro-thermal simulation of SOI circuits.

11.

Thermally generated leakage current mechanisms of metal-induced laterally crystallized n-type poly-Si TFTs under hot-carrier stress   Original Research Article Pages 62-66 Zhen Zhu Highlights ► The TG leakage current under the HC stress decreases due to the ‘‘DRME” mechanism. ► The TG leakage current under the HC stress increases due to the “TIE” mechanism. ► The larger the stress-Vd or TFTs’ size is, the easier the “DRME” occurs. ► The increment of the TG leakage current follows the Schottky model. ► The ‘‘DRME” is the dominant mechanism in the TG leakage current under the HC stress.

12.

Study of nitrogen impact on VFB–EOT roll-off by varying interfacial SiO2 thickness   Original Research Article Pages 67-71 Moonju Cho, Amal Akheyar, Marc Aoulaiche, Robin Degraeve, Lars-Åke Ragnarsson, Joshua Tseng, Thomas Y. Hoffmann, Guido Groeseneken Highlights ► VFB increases when interfacial layer decreases due to the higher trap density near the interface. ► Higher concentration of nitrogen atom diffusion introduces higher interfacial trap density. ► The VFB roll-off can be improved by process development reducing nitrogen diffusion.

13.

The performance improvement evaluation for SiGe-based IR detectors   Original Research Article Pages 72-76 M. Kolahdouz, A. Afshar Farniya, M. Östling, H.H. Radamson Research highlights ► The SNR in IR detectors increases significantly by integrating Ni silicide contacts. ► The silicidation slightly improves TCR values for the detectors (+0.22%/K). ► Increasing the Ge content of the wells has the most significant effect on the TCR.

14.

The influence of visible light on the gate bias instability of In–Ga–Zn–O thin film transistors   Original Research Article Pages 77-81 Sangwook Kim, Sunil Kim, Changjung Kim, JaeChul Park, Ihun Song, Sanghun Jeon, Seung-Eon Ahn, Jin-Seong Park, Jae Kyeong Jeong Highlights ► Gate bias instability of a-IGZO TFTs under visible lights (red, green, blue, white and dark). ► Investigating positive and negative gate bias instability effects systematically. ► Compensation effect of the electron carrier trapping and the creation of meta-stable donors via photon excitation.

15.

Investigation of scalability of In0.7Ga0.3As quantum well field effect transistor (QWFET) architecture for logic applications   Original Research Article Pages 82-89 E. Hwang, S. Mookerjea, M.K. Hudait, S. Datta Highlights ► The scalability of In0.7Ga0.3As QWFETs for 15 nm node and beyond logic applications is investigated. ► Excellent agreements between experimental measurements and drift–diffusion simulation results have been demonstrated. ► The significance of source side injection velocity is emphasized for short channel length III-V QWFETs operating in quasi ballistic mode. ► Of QWFET architectures investigated, double gate QWFET achieves the best logic figure of merit from both transport and scalability standpoint.

16.

Bipolar switching characteristics of low-power Geo resistive memory   Original Research Article Pages 90-93 C.H. Cheng, P.C. Chen, S.L. Liu, T.L. Wu, H.H. Hsu, Albert Chin, F.S. Yeh Highlights ► We demonstrate GeOx RRAM with both cost-effective and ultra-low power. ► Hopping conduction mechanism effectively lowers switched currents. ► Self-compliance switched mode presents from penalties of excess forming current via filaments. ► Size-related switched power enables application of high-density memory.

17.

Hot-electron induced degradations in GaN-based LEDs fabricated on nanoscale epitaxial lateral overgrown layers   Original Research Article Pages 94-98 Z.W. Zhang, C.F. Zhu, W.K. Fong, K.K. Leung, P.K.L. Chan, C. Surya Highlights ► Fabrication of nano-scale SiO2 growth mask using self-formed Ni clusters. ► Growth of the GaN nano-ELOG layer. ► Fabrication of GaN/InGaN multiple quantum wells on top of the nano-ELOG layer. ► Characterization of the optoelectronic properties of the MQW. ► Investigation of hot-electron degradation in the device.

18.

Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS   Original Research Article Pages 99-105 Rodrigo Trevisoli Doria, Eddy Simoen, Cor Claeys, João Antonio Martino, Marcelo Antonio Pavanello Research highlights ► HD3 of 2-MOS structures composed by FinFETs reduces with the raise of the gate bias. ► HD3 reduction is more pronounced in narrower and longer devices. ► HD3 is associated to the mobility degradation related to phonon scattering. ► Use of strained FinFETs reduces slightly HD3 and strongly the on-resistance.

19.

Buried-Pt gate InP/In0.52Al0.48As/In0.7Ga0.3As pseudomorphic HEMTs   Original Research Article Pages 106-109 Seung Heon Shin, Tae-Woo Kim, Jong-In Song, Jae-Hyung Jang Research highlights ► InP based p-HEMTs were fabricated by using buried-Pt gate on the 6-nm InP layer. ► Pt atoms penetrated the InP layer and made Schottky contact on the InAlAs layer. ► Pt atoms reacted with the InAlAs layer to form a PtAs2 alloy. ► PtAs2 alloy enhanced the Schottky barrier height. ► Buried-Pt gate on the InP layer improved the DC, RF and switching performances.

20.

Solution processed inverter based on zinc oxide nanoparticle thin-film transistors with poly(4-vinylphenol) gate dielectric   Original Research Article Pages 110-114 K. Wolff, U. Hilleringmann Research highlights ► ZnO nanoparticles are used as semiconducting material in low-cost TFT. ► The integration technique is simple and compatible to plastic substrates. ► Inverters based on nanoparticle-TFTs are functional blocks for low-cost circuits. ► The inverter performance is partially superior to competing devices.

21.

MOSFET modeling for design of ultra-high performance infrared CMOS imagers working at cryogenic temperatures: Case of an analog/digital 0.18 μm CMOS process   Original Research Article Pages 115-122 P. Martin, A.S. Royet, F. Guellec, G. Ghibaudo Research highlights ► Specific physical effects are observed in a cooled (77–200 K) 0.18 μm CMOS process. ► These effects are described and modeled for design of cryogenic IR CMOS imagers. ► Data on low frequency noise and transistor matching in MOSFET are also presented.

22.

Generalization of the van der Pauw relationship derived from electrostatics   Original Research Article Pages 123-127 Jonathan D. Weiss Highlights ► A van der Pauw result is presented for an electrode array smaller than the sample. ► The consequences of this modified arrangement are presented. ► Its disadvantages relative to the original van der Pauw arrangement are discussed. ► As a consequence of this work, a new mathematical relationship has been uncovered. ► This electrostatics technique can be applied to the calculation of the Hall voltage.

23.

Improvement on low-temperature deposited HfO2 film and interfacial layer by high-pressure oxygen treatment   Original Research Article Pages 128-131 Po-Chun Yang, Ting-Chang Chang, Shih-Ching Chen, Hsuan-Hsiang Su, Jin Lu, Hui-Chun Huang, Der-Shin Gan, New-Jin Ho Highlights ► High-pressure oxygen treatments effectively improve the properties of HfO2 film. ► From XPS analyses, the O–Hf and O–Hf–Si bonding energies raise apparently. ► After O2+ UV light treatment, the leakage current density exhibit two orders decrease. ► The conduction mechanism was transformed from trap-assisted tunneling to Schottky emission. ► This low temperature and high pressure oxygen treatment is applicable for the flexible electronics.

24.

Germanium vertical Tunneling Field-Effect Transistor   Original Research Article Pages 132-137 D. Hähnel, M. Oehme, M. Sarlija, A. Karmous, M. Schmid, J. Werner, O. Kirfel, I. Fischer, J. Schulze Highlights ► We report on the first realization of a pure Ge bulk vertical TFET. ► We compare the performance of a pure Ge bulk vTFET with a pure Si bulk vTFET. ► We examine that the main transport mechanism in the vTFETs is due to BTB tunneling.

25.

Study of Shubnikov–de Haas oscillations and measurement of hole effective mass in compressively strained InXGa1−XSb quantum wells   Original Research Article Pages 138-141 Aneesh Nainani, Toshifumi Irisawa, Brian R. Bennett, J. Brad Boos, Mario G. Ancona, Krishna C. Saraswat Highlights ► InGaSb has the highest hole mobility amongst III-V’s which can be enhanced further using strain. ► Strain ; confinement in InGaSb quantum well splits light/heavy hole bands leading to reduction in the hole effective mass. ► Magnetotransport measurements were performed on compressively-strained InGaSb and GaSb quantum wells. ► Hole effective mass was measured using Shubnikov–de Haas oscillations. ► Reduction of effective hole mass with strain was quantified. Experimental data show excellent match with modeling results.

26.

Effect of AlInGaN barrier layers with various TMGa flows on optoelectronic characteristics of near UV light-emitting diodes grown by atmospheric pressure metalorganic vapor phase epitaxy   Original Research Article Pages 142-145 Yi-Keng Fu, Yu-Hsuan Lu, Ren-Hao Jiang, Bo-Chun Chen, Yen-Hsiang Fang, Rong Xuan, Yan-Kuin Su, Chia-Feng Lin, Jebb-Fang Chen Highlights ► Near ultraviolet light-emitting diodes with quaternary AlInGaN quantum barriers (QB). ► The indium mole fraction of AlInGaN QB could be enhanced as we increased the TMG flow rate. ► Under 300 mA current injection, the LED output power with Al0.089In0.035Ga0.876N QB can be enhanced by 15.9%. ► A reduction of lattice mismatch induced polarization mismatch in the active layer by using AlInGaN QB.

27.

Influence of the sidewall crystal orientation, HfSiO nitridation and TiN metal gate thickness on n-MuGFETs under analog operation   Original Research Article Pages 146-151 M. Rodrigues, M. Galeti, J.A. Martino, N. Collaert, E. Simoen, C. Claeys Highlights ► HfSiO dielectric/TiN metal gate and rotated layout in MuGFET devices for analog application. ► Thinner TiN metal gate achieve a larger intrinsic voltage gain. ► HfSiON dielectric presented reduced Early voltage resulting in degraded analog behavior. ► MuGFET devices with rotated layout showed larger mobility and smaller Early voltage.

28.

Comparative study of AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors with Al2O3 and HfO2 gate oxide   Original Research Article Pages 152-155 Eiji Miyazaki, Yuji Goda, Shigeru Kishimoto, Takashi Mizutani Highlights ► The performance of Al2O3/AlGaN/GaN MOSHFETs and HfO2/AlGaN/GaN MOSHFETs was compared. ► The fabrication process was identical except the gate oxide deposited by ALD. ► The interface quality was better in Al2O3/AlGaN/GaN MOSHFETs than in HfO2/AlGaN/GaN MOSHFETs. ► The gate leakage current was five to eight orders of magnitude smaller in the Al2O3 MOSHFETs.

29.

Design, fabrication, and evaluation of a 5 F–5 V prototype of solid-state PANI based supercapacitor   Original Research Article Pages 156-160 M.M. Khandpekar, R.K. Kushwaha, S.P. Pati Graphical abstract The fabricated 5 F- 5V prototype of supercapacitor. Highlights ► A 5 F–5 V prototype supercapacitor based on cross linked polymer electrolyte (PANI) and XSPEEK. ► Scale-up from a small single cell to a larger stack prototype of a solid-state supercapacitor. ► Shows a higher series resistance than estimated and achieved a specific capacitance of 480 F/g. ► A maximum capacitance of 4.67 F has been obtained for the device. ► Higher capacitance at very low frequencies of order of 0.01 F falling by 25% at 0.1 Hz.

30.

Analysis of “on” and “off” times for thermally driven VO2 metal-insulator transition nanoscale switching devices   Original Research Article Pages 161-164 Yan Zhang, Shriram Ramanathan Highlights ► We estimate the switching characteristics of thermally-driven two-terminal VO2 devices. ►We use a simple resistance-capacitance thermal circuit model to explore the minimum switching time for both heating and cooling processes. ► Our study shows that the estimated switching time is on the order of ∼1ns for 20 nm VO2 films.

31.

Physics-based compact model for ultra-scaled FinFETs   Original Research Article Pages 165-173 Ashkhen Yesayan, Fabien Prégaldiny, Nicolas Chevillon, Christophe Lallement, Jean-Michel Sallese Highlights ► We propose a physical and explicit compact model for lightly doped FinFETs. ► This design-oriented model is valid for a large range of silicon Fin widths/lengths. ► It describes well the drain current, small signal parameters and capacitances. ► It takes into account all short-channel effects and quantum mechanical effects. ► This compact model needs a very few number of electrical parameters (4).

32.

Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET’s   Original Research Article Pages 174-184 Krishna Meel, R. Gopal, Deepak Bhatnagar Highlights ► New 3-D front (back) gate threshold voltage models of FD-SOI MOSFETs are reported. ► Models solve 3-D Poisson’s equation using Green’s function as a tool. ► 3-D threshold voltage models include side wall, source/drain and back gate effects. ► Front and back gate charge coupling is incorporated in both the threshold voltages. ► Compact models of threshold voltages are amenable to circuit CAD tool.

33.

High mobility compressive strained Si0.5Ge0.5 quantum well p-MOSFETs with higher-k/metal-gate   Original Research Article Pages 185-188 W. Yu, B. Zhang, Q.T. Zhao, J.-M. Hartmann, D. Buca, A. Nichau, R. Lupták, J.M. Lopes, S. Lenk, M. Luysberg, K.K. Bourdelle, X. Wang, S. Mantl Highlights ► We fabricate compressively strained Si0.5Ge0.5 quantum well p-MOSFETs. ► LaLuO3 with k ∼ 30 is successfully integrated in the device as gate dielectric. ► The hole mobility is about 2.5 times higher than the Si universal hole mobility. ► Devices with LaLuO3 and HfO2 show similar hole mobilities. ► The hole mobility degradation with high-k is much less than electrons.

34.

High quality relaxed Ge layers grown directly on a Si(0 0 1) substrate   Original Research Article Pages 189-194 V.A. Shah, A. Dobbie, M. Myronov, D.R. Leadley Highlights ► Ge surface roughness, relaxation and threading dislocation density are studied. ► A transition from compressive to tensile strain is shown. ► Tensile strain of high temperature layers can be controlled. ► Thin layers show surface roughnesses of the order of 2 Å prior to annealing. ► Thick structures are required for both low surface roughness and a lower TDD.

35.

Mobility analysis of surface roughness scattering in FinFET devices   Original Research Article Pages 195-201 Jae Woo Lee, Doyoung Jang, Mireille Mouis, Gyu Tae Kim, Thomas Chiarella, Thomas Hoffmann, Gérard Ghibaudo Highlights ► Mobility analysis of the surface roughness scattering along the different interfaces of FinFET devices. ► The sidewall and top surface drain current components were estimated from the total drain currents of different fin width conditions. ► The contribution of the surface roughness scattering was analysed and that on sidewalls was about three times stronger than on top surface for n-channel FinFETs.

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