ScienceDirect Alert: Solid-State Electronics, Vol. 60, Iss. 1, 2011

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Solid-State Electronics Volume 60, Issue 1,  Pages 1-138 (June 2011) Papers Selected from the 5th International SiGe Technology and Devices Meeting (ISTDM 2010) Edited by Mikael Ostling, B. Gunnar Malm and Henry H. Radamson Modify or Remove My Alerts

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Editorial Board    Page IFC

Editorial

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Foreword    Page 1 Mikael Östling, B. Gunnar Malm, Henry H. Radamson

Topical Area: Epitaxial Growth and Characterization

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Low threading dislocation density Ge deposited on Si (1 0 0) using RPCVD   Original Research Article Pages 2-6 Yuji Yamamoto, Peter Zaumseil, Tzanimir Arguirov, Martin Kittler, Bernd Tillack Graphical abstract Threading dislocation density as function of Ge thickness deposited with different annealing processes. AFM images of 4.7 μm thick Ge deposited without annealing process and Ge deposited with cyclic annealing process. Research highlights ► Smooth Ge layer growth on Si (1 0 0) surface without graded SiGe buffer is performed using RPCVD. ► Threading dislocation density (TDD) is decreased with increasing Ge thickness. ► TDD is decreased by postannealing and further decease is observed by cyclic annealing. ► TDD of 7 × 105 cm−2 without degrading surface roughness is achieved.

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Al-Induced oriented-crystallization of Si films on quartz and its application to epitaxial template for Ge growth   Original Research Article Pages 7-12 Masashi Kurosawa, Kaoru Toko, Naoyuki Kawabata, Taizoh Sadoh, Masanobu Miyao Research highlights ► We report systematic study of Al-induced crystallization (AIC) of Si. ► We clarify AIC conditions to control preferential orientation, i.e., (1 0 0) or (1 1 1). ► We demonstrate epitaxial growth of Ge layers using AIC-Si templates.

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Solid-phase epitaxy of amorphous silicon films by in situ postannealing using RPCVD   Original Research Article Pages 13-17 Oliver Skibitzki, Yuji Yamamoto, Markus Andreas Schubert, Günter Weidner, Bernd Tillack Graphical abstract Lateral length of crystallized epi-Si from amorphous Si on Si3N4/SiO2 mask by Solid-phase epitaxy (SPE) is investigated. 500 nm of crystallized epi-Si domain on the mask is formed by 575 °C postannealing. The defects in the crystallized epi-Si are reduced by following 1000°C annealing. Research highlights ► Solid-phase epitaxy (SPE) of amorphous Si on patterned Si(001) by RPCVD was studied. ► Lateral SPE length grew with increasing postannealing temperature. ► Lateral SPE length grew with increasing postannealing time and saturates after 1 h. ► ∼500 nm of amorphous Si on mask was crystallized to epitaxial Si (epi-Si) at 575°C. ► By 2nd postannealing at 1000°C, defects in crystalized epi-Si is drastically reduced.

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Growth-direction-dependent characteristics of Ge-on-insulator by Si–Ge mixing triggered melting growth   Original Research Article Pages 18-21 Y. Ohta, T. Tanaka, K. Toko, T. Sadoh, M. Miyao Research highlights ► Melting growth technique is investigated to obtain Ge layers on insulators (GOI). ► Growth-direction-dependent growth characteristics are clarified. ► Large area GOI with a mesh-pattern is demonstrated. ► This technique is useful to realize advanced transistors.

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Strained single-crystal GOI (Ge on Insulator) arrays by rapid-melting growth from Si (1 1 1) micro-seeds   Original Research Article Pages 22-25 T. Sakane, K. Toko, T. Tanaka, T. Sadoh, M. Miyao Highlights ► Melting growth of Ge layers on insulators (GOI) is investigated. ► Ni-imprint-induced Si (1 1 1) micro-crystals are employed as seed. ► Single-crystalline GOI (1 1 1) with large area (∼10 μmϕ) is realized. ► The tensile strain (∼0.2%) which enhances the carrier mobility is induced. ► This new method can be employed to realize the multi-functional SiGe LSI.

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X-ray microdiffraction investigation of crystallinity and strain relaxation in Ge thin lines selectively grown on Si(0 0 1) substrates   Original Research Article Pages 26-30 Kouhei Ebihara, Jun Kikkawa, Yoshiaki Nakamura, Akira Sakai, Gang Wang, Matty Caymax, Yasuhiko Imai, Shigeru Kimura, Osami Sakata Research highlights ► Selective growth of Ge thin lines with widths of 100, 200, 500 and 1000 nm on Si substrates. ► Crystal domains with small tilt angles exist in the as-grown Ge lines for the four line widths. ► The tilt angle range of the domain is larger in thinner Ge lines. ► Single domain with a specific tilt angle exists in 100- and 200- nm width Ge lines after annealing. ► SiO2 side walls around the Ge thin lines can affect crystallinity and strain relaxation of Ge.

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Study of Arsenic ion implantation of patterned strained Si NWs   Original Research Article Pages 31-36 R.A. Minamisawa, S. Habicht, L. Knoll, Q.T. Zhao, D. Buca, S. Mantl, F. Köhler, R. Carius Research highlights ► The formation of highly doped strained Si NWs and layers on insulator is presented. ► Patterning of doped layers results in perfect crystalline doped strained Si NWs. ► Direct implantation of NWs at RT induces strong strain relaxation. ► Elastic strain is conserved by high temperature implantation. ► Dopant out-diffusion occurs during direct implantation of NWs.

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Subband structure and effective mass of relaxed and strained Ge (1 1 0) PMOSFETs   Original Research Article Pages 37-41 Bing-Fong Hsieh, Shu-Tong Chang Research highlights ► Simple and useful effective mass information for quasi two dimension hole transport. ► A new guideline for a novel CMOS design. ► Impact of (1 1 0) surface orientation on hole transport in a Ge inversion layer.

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Non-destructive thickness characterization of Si based heterostructure by X-ray diffraction and reflectivity   Original Research Article Pages 42-45 Xue-Chao Liu, M. Myronov, A. Dobbie, Van H. Nguyen, D.R. Leadley Graphical abstract Highlights ► High-resolution X-ray diffraction rocking curve (RC), X-ray reflectivity (XRR) and transmission electron microscopy (TEM) are used to characterize the Si based heterostructures. The reliability and accuracy of thickness measurement are analysed by the different techniques. ► Both XRR and RC produce reliable values that agree well with transmission electron microscope (TEM) results over a wide range for smooth Si epilayers grown on a thin (20 nm) strained Si0.9Ge0.1 buffer. The best-fit thickness from both XRR and RC is within ±5% of the TEM measurement, with XRR producing more accurate values than RC. ► The agreement is not good for rough Si epilayer grown on a thick (2 μm) relaxed Si07Ge0.3 virtual substrate due to the presence of rough surface.

Topical Area: Device Related Materials

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Formation of Ni(Ge1−xSnx) layers with solid-phase reaction in Ni/Ge1−xSnx/Ge systems   Original Research Article Pages 46-52 Tsuyoshi Nishimura, Osamu Nakatsuka, Yosuke Shimura, Shotaro Takeuchi, Benjamin Vincent, Andre Vantomme, Johan Dekoster, Matty Caymax, Roger Loo, Shigeaki Zaima Research highlights ► Formation of nickel-tin-germanide contacts for germanium-tin source/drain stressors. ► Reaction products after the solid phase reaction of Ni/Ge1−xSnx systems with various Sn contents. ► Sn precipitation from Ni(Ge1−xSnx) layers with annealing. ► Agglomeration behavior of Ni(Ge1−xSnx) layers on Ge1−xSnx layers. ► Strain behavior of Ge1−xSnx layers after the germanidation process for contact formation.

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Ge1−xSnx stressors for strained-Ge CMOS   Original Research Article Pages 53-57 S. Takeuchi, Y. Shimura, T. Nishimura, B. Vincent, G. Eneman, T. Clarysse, J. Demeulemeester, A. Vantomme, J. Dekoster, M. Caymax, R. Loo, A. Sakai, O. Nakatsuka, S. Zaima Research highlights ► GeSn materials have potential for strained Ge pMOSFET. ► p-type doped GeSn growth and Ni(GeSn) formation which can be used in the source/drain area have been successfully demonstrated. ► These layer qualities strongly depends on thermal budget.

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Improving the high-frequency performance of SiGe HBTs by a global additional uniaxial stress   Original Research Article Pages 58-64 Thanh Viet Dinh, Sung-Min Hong, Christoph Jungemann Research highlights ► A global additional uniaxial stress ranging from −1 GPa to 1 GPa has been applied to SiGe HBTs including a slow one (peak fT = 110 GHz) and a fast one (peak fT = 750 GHz). ► Full-band Monte Carlo and spherical-harmonics-expansion simulators have been used together to investigate such stressed devices. ► The simulation results show that the cutoff frequency of both devices can be improved by more than 30 percent under suitable stress conditions. ► The transit times at all regions (base, collector, emitter) of these HBTs are reduced.

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High-density formation of Ge quantum dots on SiO2   Original Research Article Pages 65-69 Katsunori Makihara, Mitsuhisa Ikeda, Akio Ohta, Shotaro Takeuchi, Yosuke Shimura, Shigeaki Zaima, Seiichi Miyazaki Research highlights ► We formed high-density Ge-QDs on an ultrathin SiO2 layer by controlling the early stages of LPCVD with GeH4 assisted by a remote H2 plasma. ► Hydrogen radicals play roles in both creation of nucleation sites on OH-terminated SiO2 surfaces and in decomposition of GeH4 to generate the precursors of Ge-QDs. ► The surface potential of the dots changed in a stepwise manner with respect to the tip bias due to multistep electron injection into and extraction from the Ge-QDs. ► These results provide useful information for the fabrication of multi-valued floating gate memories.

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Control of interfacial properties of Pr-oxide/Ge gate stack structure by introduction of nitrogen   Original Research Article Pages 70-74 Kimihiko Kato, Hiroki Kondo, Mitsuo Sakashita, Osamu Nakatsuka, Shigeaki Zaima Research highlights ► Controlling interfacial properties of Pr-oxide/Ge structures by the introduction of nitrogen. ► Nitrogen component segregates at the Pr-oxide/Ge interface. ► Formation of Pr-oxide/PrON/Ge structures without Ge-oxide or Ge-oxynitride interlayer. ► Interface state density as low as 4 × 1011 eV−1 cm−2.

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Integration of MOSFETs with SiGe dots as stressor material   Original Research Article Pages 75-83 L.K. Nanver, V. Jovanović, C. Biasotto, J. Moers, D. Grützmacher, J.J. Zhang, N. Hrauda, M. Stoffel, F. Pezzoli, O.G. Schmidt, L. Miglio, H. Kosina, A. Marzegalli, G. Vastola, G. Mussler, J. Stangl, G. Bauer, J. van der Cingel, E. Bonera Highlights ► DotFETs – first experimental n-channel MOSFETs fabricated on SiGe dots. ► SiGe dots grown in an S–K mode used as source of stress for mobility enhancement. ► Low-complexity, custom-made low-temperature (Tmax = 400 °C) process. ► Laser-annealed source/drain regions self-aligned to gate. ► Average increase in drain current up to 22.5%.

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Control of strain relaxation behavior of Ge1−xSnx buffer layers   Original Research Article Pages 84-88 Yosuke Shimura, Shotaro Takeuchi, Osamu Nakatsuka, Akira Sakai, Shigeaki Zaima Research highlights ► Control of strain relaxation behavior in Ge1-xSnx layers by the misfit strain. ► Dependence of crystallinity of Ge1-xSnx layers on the misfit strain. ► Fully strain relaxed Ge1-xSnx layer with Sn content of 9.2% grown on a Si substrate. ► The Ge1-xSnx layer having a potential to induce a tensile strain of 0.99% to a Ge layer.

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Introduction of local tensile strain on Ge substrates by SiGe stressors selectively grown on wet chemically recessed regions for strained Ge-nMOSFETs   Original Research Article Pages 89-92 Yoshihiko Moriyama, Yuuichi Kamimuta, Keiji Ikeda, Tsutomu Tezuka Highlights ► Uni-axial tensile strain is applied to Ge for high-mobility Ge-nMOSFETs. ► Anisotropic wet etching for damage-less Ge recess formation. ► Sufficient strain over 1% in Ge for 4 times higher electron-mobility than Si.

Topical Area: Opto-electronic and Novel Devices

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Double-polysilicon SiGe HBT architecture with lateral base link   Original Research Article Pages 93-99 A. Fox, B. Heinemann, H. Rücker Research highlights ► We present a novel double polysilicon SiGe HBT technology. ► We achieve fT/fmax of 300GHz/350GHz and a ring oscillator gate delay of 2.5ps. ► Technological challenges for further device scaling are adressed.

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SiGe/Si quantum structures as a thermistor material for low cost IR microbolometer focal plane arrays   Original Research Article Pages 100-104 J.Y. Andersson, P. Ericsson, H.H. Radamson, S.G.E. Wissmar, M. Kolahdouz Research highlights ► Monocrystalline SiGe/Si superlattices are suggested as a thermistors for infrared bolometers. ► Proper design of a SiGe/Si superlattices enables sensing with high signal-to-noise ratio. ► SiGe is compatible with microelectronics processing enabling manufacturing at lower cost.

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Germanium photodetectors on Silicon-on-insulator grown with differential molecular beam epitaxy in silicon wells   Original Research Article Pages 105-111 M. Kaschel, M. Schmid, M. Oehme, J. Werner, J. Schulze Research highlights ► We successfully fabricated vertical Germanium pin photodetectors in Silicon wells by using differential molecular beam epitaxy and chemical mechanical polishing. ► As the electrical properties indicate, the grown layers have a good crystal quality and external cut-off frequencies of over 20 GHz are achieved. ► The measured broad spectral range and the energy of the direct band edge leads to the conclusion that the new process does not increase the strain in the active Germanium absorption layer compared to conventional fabricated detectors.

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Fabrication of high-Ge-fraction strained Si1−xGex/Si hole resonant tunneling diode using low-temperature Si2H6 reaction for nanometer-order ultrathin Si barriers   Original Research Article Pages 112-115 Kuniaki Takahashi, Masao Sakuraba, Junichi Murota Research highlights ► Fabrication of high-Ge-fraction strained Si1−xGex/Si hole resonant tunneling diodes. ► Low-temperature Si barrier growth with atomically flat heterointerfaces. ► Si2H6 reaction at 400 °C on Si0.42Ge0.58 in low-pressure chemical vapor deposition. ► Improvement in negative differential conductance characteristics at room temperature. ► Thermionic-emission dominant characteristics at higher temperatures above 100 K.

Topical Area: Process Technology

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Si passivation for Ge pMOSFETs: Impact of Si cap growth conditions   Original Research Article Pages 116-121 B. Vincent, R. Loo, W. Vandervorst, J. Delmotte, B. Douhard, V.K. Valev, M. Vanbel, T. Verbiest, J. Rip, B. Brijs, T. Conard, C. Claypool, S. Takeuchi, S. Zaima, J. Mitard, B. De Jaeger, J. Dekoster, M. Caymax Research highlights ► Impact of Si cap Ge passivation pn Ge pMOSFETs performances. ► Impact of RPCVD Si growth process conditions on Si crystallinity and Ge segregation. ► Offers the best route for Ge passivation.

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Fabrication of Ge-MOS capacitors with high quality interface by ultra-thin SiO2/GeO2 bi-layer passivation combined with the subsequent SiO2-depositions using magnetron sputtering   Original Research Article Pages 122-127 Kana Hirayama, Keisuke Yoshino, Ryuji Ueno, Yoshiaki Iwamura, Haigui Yang, Dong Wang, Hiroshi Nakashima Research highlights ► We fabricated Ge-MOS capacitors by SiO2/GeO2 bi-layer passivation for Ge surface. ► We obtained good C–VG and J–E characteristics for typical Ge-MOS capacitors. ► We obtained Dit of 4 × 1011 cm−2 eV−1 at around mid-gap for Al-gate Ge-MOS capacitor. ► Bi-layer passivation with O2 improves interface quality for Ge-MOS gate stack.

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Effective passivation of defects in Ge-rich SiGe-on-insulator substrates by Al2O3 deposition and subsequent post-annealing   Original Research Article Pages 128-133 Haigui Yang, Masatoshi Iyota, Shogo Ikeura, Dong Wang, Hiroshi Nakashima Research highlights ► Al2O3-PDA was proposed to passivate electrically active defects in Ge-rich SGOI. ► Al2O3-PDA effectively suppressed the surface reaction during Al-PDA. ► Al2O3-PDA reduced the defect-induced acceptor concentration in Ge-rich SGOI. ► Al2O3-PDA greatly improves the electrical characteristics of Ge-rich SGOI.

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Control of topography and morphology for channel SiGe by in-situ HCl etching for future CMOS technologies with high-K metal gate   Original Research Article Pages 134-138 Carsten Reichel, Stephan Kronholz, Thorsten Kammler, Annekathrin Zeun, Gunda Beernink Research highlights ► A SiGe epi layer in the P-channel is applied to modulate VT. ► This results in an unwanted elevation of P-channel. ► In-situ HCl etching prior to epi deposition reduces topography. ► Topography driven leakage current has been reduced by one order of magnitude.

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