| | 2. | Foreword
Page 1
Damien Deleruyelle, Giuseppe Iannaccone
| | | | 4. | Impact of Ge–Sb–Te compound engineering on the set operation performance in phase-change memories Original Research Article
Pages 11-16
Mattia Boniardi, Daniele Ielmini, Innocenzo Tortorelli, Andrea Redaelli, Agostino Pirovano, Mario Allegra, Michele Magistretti, Camillo Bresolin, Davide Erbetta, Alberto Modelli, Enrico Varesi, Fabio Pellizzer, Andrea L. Lacaita, Roberto Bez
Research highlights► The reported research is very attractive in order to enlarge the possible PCM application spectrum. ► The introduction of an increasing antimony (Sb) concentration has the effect of making the set operation more efficient. ► An increasing operation current has been ascribed to an increasing average coordination number or to a change in network connectivity/topology induced by the Sb-enrichment. ► A decreasing program window, as well as threshold voltage, has been related to a decreasing energy gap in the amorphous phase of Ge–Sb–Te alloys with higher Sb concentration. ► A better performance in terms of the reset-to-set transition has been interpreted in the framework of the crystallization kinetics, invoking a growth-driven mechanism induced by a higher Sb concentration.
| | | | 5. | A fast and reliable method used to investigate the size-dependent retention lifetime of a phase-change line cell Original Research Article
Pages 17-22
L. Goux, G.A.M. Hurkx, X.P. Wang, R. Delhougne, K. Attenborough, D. Gravesteijn, D. Wouters, J. Perez Gonzalez
Research highlights► We model the temperature-dependent resistance of a fast-growth phase-change cell. ► We obtain excellent match assuming crystal growth from the amorphous/crystal front. ► A single temperature ramp allows the extraction of retention characteristics. ► Using this method we predict a limited lifetime reduction with cell downscaling.
| | | | 6. | Empirical investigation of SET seasoning effects in Phase Change Memory arrays Original Research Article
Pages 23-27
C. Zambelli, A. Chimenton, P. Olivo
Research highlights► We present the SET seasoning phenomenon in Phase Change Memory (PCM) arrays. ► We characterized the SET seasoning in relation to the erasing scheme exploited in PCM. ► We provided a detailed physical explanation to the SET seasoning. ► We defined a quantitative metric for the SET seasoning impact estimation on PCM.
| | | | 7. | Highly-scalable disruptive reading and restoring scheme for Gb-scale SPRAM and beyond Original Research Article
Pages 28-33
R. Takemura, T. Kawahara, K. Ono, K. Miura, H. Matsuoka, H. Ohno
Research highlights► We proposed a disruptive reading and restoring scheme for a gigabit scale SPRAM. ► Basic operation was confirmed by using a 32-Mb SPRAM chip. ► DDR SDRAM compatible SPRAM operation using the proposed scheme was proposed. ► We presented a 4F2 cell structure and prospect of the reliability of the TMR device.
| | | | 10. | Flexible and transparent ReRAM with GZO memory layer and GZO-electrodes on large PEN sheet Original Research Article
Pages 48-53
K. Kinoshita, T. Okutani, H. Tanaka, T. Hinoki, H. Agura, K. Yazawa, K. Ohmi, S. Kishida
Research highlights► Low temperature formation of GZO films with arbitrary resistivity. ► Fabrication of all-GZO-based flexible and transparent ReRAM on a large plastic film. ► High memory performance such as compatibility for multilevel application was confirmed.
| | | | 11. | Demonstration of Conductive Bridging Random Access Memory (CBRAM) in logic CMOS process Original Research Article
Pages 54-61
C. Gopalan, Y. Ma, T. Gallo, J. Wang, E. Runnion, J. Saenz, F. Koushan, P. Blanchard, S. Hollmer
Research highlights► Successful Integration of CBRAM technology in standard logic CMOS process. ► Demonstrated Low operational voltages , currents, and ultra fast switching. ► Demonstrated Robust noise immunity, good retention and cycling endurance. ► CBRAM technology is ideal for low power and embedded Non Volatile Memories.
| | | | 12. | Comparative study of non-polar switching behaviors of NiO- and HfO2-based oxide resistive-RAMs Original Research Article
Pages 62-67
V. Jousseaume, A. Fantini, J.F. Nodin, C. Guedj, A. Persico, J. Buckley, S. Tirano, P. Lorenzi, R. Vignon, H. Feldis, S. Minoret, H. Grampeix, A. Roule, S. Favier, E. Martinez, P. Calka, N. Rochat, G. Auvert, J.P. Barnes, P. Gonon, C. Vallée, L. Perniola, B. De Salvo
Research highlights► Resistive memories with NiO or HfO2 as active materials and Pt electrodes. ► Devices fabricated with identical integration scheme. ► Both oxides present non-polar switching. ► HfO2 devices lead to largest High Resistance State/Low Resistance State ratios. ► Electrical data are consistent with the filamentary hypothesis.
| | | | 13. | Investigation of charge-trap memories with AlN based band engineered storage layers Original Research Article
Pages 68-74
G. Molas, J.P. Colonna, R. Kies, D. Belhachemi, M. Bocquet, M. Gély, V. Vidal, P. Brianceau, E. Martinez, A.M. Papon, C. Licitra, L. Vandroux, G. Ghibaudo, B. De Salvo
| | | | 14. | Modeling of program, erase and retention characteristics of charge-trap gate all around memories Original Research Article
Pages 75-82
Etienne Nowak, Luca Perniola, Gérard Ghibaudo, Gabriel Molas, Gilles Reimbold, Barbara De Salvo, Fabien Boulanger
Research highlights► This paper describes the effect of geometry in charge-trap memory devices. ► Impact of the curvature radius on the gate current is theoretically analyzed. ► Nanocrystal and SONOS GAA program, erase and retention behaviors are explained. ► Cylindrical devices eliminate erase saturation while keeping sufficient retention.
| | | | 15. | Low power options for 32 nm always-on SRAM architecture Original Research Article
Pages 83-95
Lahcen Hamouche, Bruno Allard
Research highlights► Extension of 5T Portless Embedded-SRAM to 32 nm CMOS and beyond. ► Original operating is presented and the current-mode operation is considered. ► The proposed SRAM is dedicated for true always-on, very low power applications. ► Hard-line copy technique is introduced to as an alternative to the current sensors. ► Low power Multiplexed architecture is developed with the hard-line copy technique.
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