ScienceDirect Alert: Solid-State Electronics, Vol. 53, Iss. 7, 2009

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Solid-State Electronics Volume 53, Issue 7,  Pages 675-814 (July 2009) Papers Selected from the 38th European Solid-State Device Research Conference – ESSDERC’08 Edited by Peter Ashburn and Stephen Hall

1.

Editorial Board Page IFC

Editorial

2.

Editorial Page 675 Peter Ashburn, Stephen Hall

Invited Papers

3.

Overview and future challenges of floating body RAM (FBRAM) technology for 32 nm technology node and beyond Pages 676-683 Takeshi Hamamoto, Takashi Ohsawa

4.

Micropower energy harvesting Pages 684-693 R.J.M. Vullers, R. van Schaijk, I. Doms, C. Van Hoof, R. Mertens

Regualr Papers

5.

Comprehensive study of S/D engineering for 32 nm node CMOS in direct silicon bonded (DSB) technology Pages 694-700 N. Yasutake, A. Nomachi, H. Itokawa, T. Morooka, L. Zhang, T. Fukushima, H. Harakawa, I. Mizushima, A. Azuma, Y. Toyosihma

6.

Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi-Vt CMOS application Pages 701-705 Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Shinichi O’uchi, Yuki Ishikawa, Hiromi Yamauchi, Junichi Tsukada, Kenichi Ishii, Kunihiro Sakamoto, Eiichi Suzuki, Meishoku Masahara

7.

Drain current improvements in uniaxially strained p-MOSFETs: A Multi-Subband Monte Carlo study Pages 706-711 F. Conzatti, M. De Michielis, D. Esseni, P. Palestri

8.

A study on aggressive proximity of embedded SiGe with comprehensive source drain extension engineering for 32 nm node high-performance pMOSFET technology Pages 712-716 Hiroki Okamoto, Nobuaki Yasutake, Naoki Kusunoki, Kanna Adachi, Hiroshi Itokawa, Kiyotaka Miyano, Tatsuya Ishida, Akira Hokazono, Shigeru Kawanaka, Ichiro Mizushima, Atsushi Azuma, Yoshiaki Toyoshima

9.

Silicon on thin BOX (SOTB) CMOS for ultralow standby power with forward-biasing performance booster Pages 717-722 T. Ishigaki, R. Tsuchiya, Y. Morita, H. Yoshimoto, N. Sugii, T. Iwamatsu, H. Oda, Y. Inoue, T. Ohtou, T. Hiramoto, S. Kimura

10.

High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate Pages 723-729 K. Romanjek, L. Hutin, C. Le Royer, A. Pouydebasque, M.-A. Jaud, C. Tabone, E. Augendre, L. Sanchez, J.-M. Hartmann, H. Grampeix, V. Mazzocchi, S. Soliveres, R. Truche, L. Clavelier, P. Scheiblin, X. Garros, G. Reimbold, M. Vinet, F. Boulanger, S. Deleonibus

11.

FDSOI devices with thin BOX and ground plane integration for 32 nm node and below Pages 730-734 C. Fenouillet-Beranger, S. Denorme, P. Perreau, C. Buj, O. Faynot, F. Andrieu, L. Tosti, S. Barnola, T. Salvetat, X. Garros, M. Cassé, F. Allain, N. Loubet, L. Pham-Nguyen, E. Deloffre, M. Gros-Jean, R. Beneyton, C. Laviron, M. Marin, C. Leyris, S. Haendler, F. Leverd, P. Gouraud, P. Scheiblin, L. Clement, R. Pantel, S. Deleonibus, T. Skotnicki

12.

Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution Pages 735-740 G. Bidal, N. Loubet, C. Fenouillet-Beranger, S. Denorme, P. Perreau, D. Fleury, L. Clement, C. Laviron, F. Leverd, P. Gouraud, S. Barnola, R. Beneyton, A. Torres, C. Duluard, J.D. Chapon, B. Orlando, T. Salvetat, M. Grosjean, E. Deloffre, R. Pantel, D. Dutartre, S. Monfray, G. Ghibaudo, F. Boeuf, T. Skotnicki

13.

New floating-body effect in partially depleted SOI pMOSFET due to direct-tunneling current in the partial n+ poly gate Pages 741-745 Georges Guegan, R. Gwoziecki, P. Touret, C. Raynaud, J. Pretet, O. Gonnard, G. Gouget, S. Deleonibus

14.

Method for 3D electrical parameters dissociation and extraction in multichannel MOSFET (MCFET) Pages 746-752 C. Dupré, T. Ernst, E. Bernard, B. Guillaumot, N. Vulliet, P. Coronel, T. Skotnicki, S. Cristoloveanu, G. Ghibaudo, O. Faynot, S. Deleonibus

15.

Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation Pages 753-759 M.M.A. Hakim, L. Tan, O. Buiu, W. Redman-White, S. Hall, P. Ashburn

16.

Performance improvement in narrow MuGFETs by gate work function and source/drain implant engineering Pages 760-766 I. Ferain, R. Duffy, N. Collaert, M.J.H. van Dal, B.J. Pawlak, B. O’Sullivan, L. Witters, R. Rooyackers, T. Conard, M. Popovici, S. van Elshocht, M. Kaiser, R.G.R. Weemaes, J. Swerts, M. Jurczak, R.J.P. Lander, K. De Meyer

17.

Evaluation of statistical variability in 32 and 22 nm technology generation LSTP MOSFETs Pages 767-772 B. Cheng, S. Roy, A.R. Brown, C. Millar, A. Asenov

18.

A 65 nm test structure for SRAM device variability and NBTI statistics Pages 773-778 Thomas Fischer, Ettore Amirante, Peter Huber, Karl Hofmann, Martin Ostermayr, Doris Schmitt-Landsiedel

19.

Electron transport through silicon serial triple quantum dots Pages 779-785 Gento Yamahata, Yoshishige Tsuchiya, Hiroshi Mizuta, Ken Uchida, Shunri Oda

20.

Impact of a HTO/Al2O3 bi-layer blocking oxide in nitride-trap non-volatile memories Pages 786-791 M. Bocquet, G. Molas, L. Perniola, X. Garros, J. Buckley, M. Gély, J.P. Colonna, H. Grampeix, F. Martin, V. Vidal, A. Toffoli, S. Deleonibus, G. Ghibaudo, G. Pananakakis, B. De Salvo

21.

Floating gate technology for high performance 8-level 3-bit NAND flash memory Pages 792-797 Tae-Kyung Kim, Sungnam Chang, Jeong-Hyuk Choi

22.

Demonstration of a wireless driven MEMS pond skater that uses EWOD technology Pages 798-802 Y. Mita, Y. Li, M. Kubota, S. Morishita, W. Parkes, L.I. Haworth, B.W. Flynn, J.G. Terry, T.-B. Tang, A.D. Ruthven, S. Smith, A.J. Walton

23.

A low-noise single-photon detector implemented in a 130 nm CMOS imaging process Pages 803-808 Marek Gersbach, Justin Richardson, Eric Mazaleyrat, Stephane Hardillier, Cristiano Niclass, Robert Henderson, Lindsay Grant, Edoardo Charbon

24.

Analysis of the DC-arc behavior of a novel 3D-active fuse Pages 809-813 J. vom Dorp, S.E. Berberich, A.J. Bauer, H. Ryssel

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