| 2. | Thermal effects in AlGaN/GaN/Si high electron mobility transistors Review Article Pages 1-6 I. Saidi, Y. Cordier, M. Chmielowska, H. Mejri, H. Maaref
Highlights► Direct-current measurements have been performed at 300 K for AlGaN/GaN/Si HEMT. ► Using a numerical method, we deduced the temperature rise in the conductive 2DEG. ► The temperature rise does not exceed 20 K. ► The temperature decreases with the drain–source spacing increase. | | | 3. | 3D-Monte Carlo study of short channel tri-gate nanowire MOSFETs Original Research Article Pages 7-12 J.K. David, L.F. Register, S.K. Banerjee
Research highlights► 3D Semiclassical Monte Carlo simulation of III–V and Si tri-gate nanowire FETs. ► Schrodinger correction with Poisson solver and non-parabolic band approximation. ► Carrier velocity as opposed to quantum/dos capacitances vary Ids between materials. ► InAs and InSb show superior performance. | | | 4. | On the characteristics of an electroless plated (EP)-based pseudomorphic high electron mobility transistor (PHEMT) Original Research Article Pages 13-17 Chien-Chang Huang, Huey-Ing Chen, Shiou-Ying Cheng, Li-Yang Chen, Tsung-Han Tsai, Yi-Chun Liu, Tai-You Chen, Chi-Hsiang Hsu, Wen-Chau Liu
Highlights► We use the EP and TE approaches to form the metal gates. ► Comparison and study on the DC and RF performance with different approaches. ► The EP approach could effectively improve the Schottky interface. ► The temperature-dependent characteristics with EP and TE approaches are demonstrated. | | | 5. | Assessment of carbon nanotube array transistors: A three-dimensional quantum simulation Original Research Article Pages 18-22 Yijian Ouyang, Jing Guo
Highlights► Performance assessment of ballistic CNT array FETs with process variations. ► Ten times and 15% larger off- and on-current for 0.24 nm diameter variation. ► Residual metallic tubes significantly increase off-current. ► Misalignment decreases on- and off-current. ► Six nanometer CNT spacing required for 2200 μA/μm on-current. | | | 6. | Characterization of laser carved micro channel polycrystalline silicon solar cell Original Research Article Pages 23-28 Hsin-Chien Chen, Liann-Be Chang, Ming-Jer Jeng, Chao-Sung Lai
Highlights► The efficiency of silicon solar cells was increased carving micro channel structures. ► Cell’s efficiency was increased 0.23–1.50% as the structure radius varied 15–35 μm. ► Efficiency started to decrease when the structure radius was greater than 40 μm. ► Micro channels also improved the Fill Factor of polycrystalline silicon solar cells. | | | 7. | Au and non-Au based rare earth metal-silicide ohmic contacts to p-InGaAs Original Research Article Pages 29-32 A. Bengi, S.J. Jang, C.I. Yeo, T. Mammadov, S. Özçelik, Y.T. Lee
Research highlights► InP/InGaAs laser diodes are potential candidates for fiber optic communication systems. ► Conventional ohmic contacts have been extensively used due to lower Schottky barrier height. ► To improve LD performance, one of the most important parameters is series resistance of the device. ► Recently, disilicides of rare earth metals have come into prominence. ► They have lower Schottky barrier height, specific contact resistivity and alloying temperature. | | | 8. | The effects of active layer thickness on Programmable Metallization Cell based on Ag–Ge–S Original Research Article Pages 33-37 F. Wang, W.P. Dunn, M. Jain, C. De Leo, N. Vickers
Research highlights► PMC devices based on Ag–Ge–S were fabricated with three thicknesses. ► The ‘ON’ resistance of PMC decreases as the active layer thickness increases. ► The SET voltage also decreases slightly as increase of the active layer thickness. ► The RESET voltage increases as increase of the active layer thickness. | | | 9. | A unified analytical and scalable lumped model of RF CMOS spiral inductors based on electromagnetic effects and circuit analysis Original Research Article Pages 38-45 Siamak Salimy, Antoine Goullet, Ahmed Rhallabi, Fatiha Challali, Serge Toutain, Jean Claude Saubat
Highlights► In this study, a compact scalable model of CMOS spiral inductors is proposed. ► The model parameters equations are expressed using simple analytical expressions. ► On chip CMOS spiral frequency dependent characteristics are modeled. ► Substrate coupling, skin and proximity effects are considered in the model. ► The model is suitable for RFIC designers and is easy to implement in design kits. | | | 11. | GaAs HEMT as sensitive strain gauge Original Research Article Pages 53-57 Jun Liu, Tingting Hou, Chenyang Xue, Zhenxin Tan, Guowen Liu, Binzhen Zhang, Wendong Zhang
Research highlights► The GaAs HEMT as the sensitive element of micro-sensors to detect the deformation. ► The maximum gauge factor of HEMT is much larger than that of piezoresistive silicon. ► The high gauge factor is due to voltage bias and piezoresistive piezoelectric effect. | | | 15. | Effect of rapid thermal annealing on pentacene-based thin-film transistors Original Research Article Pages 76-80 D.W. Chou, C.J. Huang, C.M. Su, C.F. Yang, W.R. Chen, T.H. Meen
Research highlights► The bottom contact pentacene-based thin-film transistor is treated by rapid thermal annealing. ► The pentacene molecular ordering was significantly improved though the grain size only slightly increased after the annealing temperature increases to 60 °C. ► The RTA treatment causes grain growth along the c axis and the elimination of defects and misoriented crystallites in the pentacene layer. ► The device annealed at temperature of 120 °C for 2 min exhibits properly electrical characteristics. | | | 16. | Recombination in the Ge-spiked monoemitter of the SiGe:C HBTs Original Research Article Pages 81-86 Shuzhen You, Stefaan Decoutere, Arturo Sibaja-Hernandez, Rafael Venegas, Stefaan Van Huylenbroeck, Kristin De Meyer
Research highlights► A SiGe spike in the monoemitter is used to increase Ib, hence improve BVCEO. ► We modeled the Auger and SRH recombination rate accounting for the increased Ib. ► In a sharp spike, from low to medium bias condition, SRH recombination dominates. ► In a sharp spike at high bias and in a diffused spike, Auger recombination dominates. ► A sharp spike results in the reduced effective minority carrier lifetime in the spike. | | | 19. | Device characteristics of amorphous indium gallium zinc oxide thin film transistors with ammonia incorporation Original Research Article Pages 96-99 Sheng-Yao Huang, Ting-Chang Chang, Min-Chen Chen, Shu-Wei Tsao, Shih-Ching Chen, Chih-Tsung Tsai, Hung-Ping Lo
Research highlights► We study the effect of ammonia incorporation on a-IGZO TFTs. ► The electrical characteristics of the TFTs are improved greatly by incorporating NH3. ► The improvement can be attributed to both hydrogen and nitrogen passivation effects. ► The traps at IGZO film were passivated by forming O–H and Zn–N bonds. | | | 20. | Improved characteristics for Pd nanocrystal memory with stacked HfAlO–SiO2 tunnel layer Original Research Article Pages 100-105 Tsung-Kuei Kang, Han-Wen Liu, Fang-Hsing Wang, Cheng-Li Lin, Ta-Chuan Liao, Wen-Fa Wu
Research highlights► The thermally induced traps in tunnel oxide can worsen the memory characteristics. ► The thickness ratio of HfAlO to SiO2 can affect a memory characteristic. ► N2 plasma treatment can further improve the memory characteristics. | | | 21. | Origin of low-frequency noise in pentacene field-effect transistors Original Research Article Pages 106-110 Yong Xu, Takeo Minari, Kazuhito Tsukagoshi, Jan Chroboczek, Francis Balestra, Gerard Ghibaudo
Research highlights► The low-frequency noise in pentacene OFETs exhibits 1/f type spectrum. ► Carrier number fluctuations model well accounts for the 1/f noise. ► Higher trap density is obtained in BC devices than in TC ones. ► Contact noise dominates the overall noise at strong current intensities. | | | 22. | Design and optimization of high voltage LDMOS transistors on 0.18 μm SOI CMOS technology Original Research Article Pages 111-115 G. Toulon, I. Cortés, F. Morancho, E. Hugonnard-Bruyère, B. Villard, W.J. Toren
Highlights► Power MOS transistors manufactured on a 0.18 μm SOI CMOS technology are compared by means of TCAD numerical simulations. ► The measured breakdown voltage results as a function of the handle wafer voltage are compared with TCAD numerical simulation. ► The simulations are used to explain the problems arising in the measured structures. ► Some important design parameters have a strong influence on the voltage capability. ► Some solutions are proposed in this work to improve the performances of the fabricated LDMOS structures. | | |