| | 2. | Foreword
Page 1
Raphaël Clerc, Olivier Faynot
| | | | 3. | High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs Original Research Article
Pages 2-7
C. Le Royer, J.-F. Damlencourt, B. Vincent, K. Romanjek, Y. Le Cunff, H. Grampeix, V. Mazzocchi, V. Carron, F. Némouchi, J.-M. Hartmann, C. Arvet, C. Vizioz, C. Tabone, L. Hutin, P. Batude, M. Vinet
Research highlights► Ge and Si areas were obtained on SOI wafers thanks to the Ge enrichment technique. ► DualChannel Ge–Si CMOS is demonstrated with a sub 600 °C Fully Depleted process. ► Planar GeOI pFETs and SOI nFETS with High-K metal-gate were cointegrated. ► This DualChannel Ge–Si CMOS exhibit the best hole/electron mobility configuration. ► The simultaneous salicidation and germanidation minimize the CMOS access resistance.
| | | | 4. | Fully depleted silicon on insulator MOSFETs on (1 1 0) surface for hybrid orientation technologies Original Research Article
Pages 8-12
T. Signamarcheix, F. Andrieu, B. Biasse, M. Cassé, A.-M. Papon, E. Nolot, B. Ghyselen, O. Faynot, L. Clavelier
Highlights► We examine the performances of fully-depleted transistor made on specific (1 1 0) oriented SOI. ► Impact of a deep amorphization and SPER is studied on SOI substrates. ► An alternative process to locally convert the orientation of an SOI film is studied.
| | | | 5. | Impact of SEG on uniaxially strained MuGFET performance Original Research Article
Pages 13-17
Paula Ghedini Der Agopian, Vinícius Heltai Pacheco, João Antonio Martino, Eddy Simoen, Cor Claeys
Research highlights► We study the influence of Selective Epitaxial Growth (SEG) on the strain efficiency. ► For short devices, a better performance was obtained for MuGFETs without SEG. ► For long devices, better results were obtained for MuGFETs with SEG. ► This study was performed at room and at low temperature.
| | | | 6. | Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs Original Research Article
Pages 18-24
V. Kilchytska, J. Alvarado, N. Collaert, R. Rooyackers, S. Put, E. Simoen, C. Claeys, D. Flandre
Research highlights► Effect of process-induced negative charges at the gate edges on MOSFETs performance. ► NCs at the gate edges can degrade subthreshold behavior and analog FoM of MOSFET. ► Enhanced Gmmax and apparent better SCE control can be due to NCs at the gate edges. ► Such behavior may appear in any advanced technology employing novel gate stacks. ► Complete set of device characteristics is required for a fair technology assessment.
| | | | 7. | Detailed investigation of effective field, hole mobility and scattering mechanisms in GeOI and Ge pMOSFETs Original Research Article
Pages 25-33
W. Van Den Daele, C. Le Royer, E. Augendre, J. Mitard, G. Ghibaudo, S. Cristoloveanu
Research highlights► In depth characterization of fully-depleted pMOSFET on GeOI substrates. ► A methodology to extract the empirical factor on FD-GeOI is proposed. ► We demonstrated the difference of in Ge and GeOI based pMOSFET. ► A detailed investigation of surface roughness scattering for holes in GeOI is provided. ► Correlation between interface traps and coulomb hole mobility is provided.
| | | | 9. | Double-gate 1T-DRAM cell using nonvolatile memory function for improved performance Original Research Article
Pages 39-43
Ki-Heung Park, Sorin Cristoloveanu, Maryline Bawedin, Youngho Bae, Kyoung-Il Na, Jong-Ho Lee
Research highlights► The DG 1T-DRAM cell has storage node on one gate for nonvolatile memory function. ► Experimental results show improved sensing margin and retention time. ► The larger excess of holes in the Si body induced by the electrons stored in the nitride.
| | | | 10. | Capacitor-less A-RAM SOI memory: Principles, scaling and expected performance Original Research Article
Pages 44-49
Noel Rodriguez, Sorin Cristoloveanu, Francisco Gamiz
Research highlights►We present a novel capacitor-less single-transistor memory cell. ►The cell features a body partitioning for hole storage and electron current. ►The scalability benefits from an enhanced potential difference between interfaces. ►The cell shows attractive performance in terms of current margins and retention time.
| | | | 11. | Physics of Gate Modulated Resonant Tunneling (RT)-FETs: Multi-barrier MOSFET for steep slope and high on-current Original Research Article
Pages 50-61
Aryan Afzalian, Jean-Pierre Colinge, Denis Flandre
Research highlights► Physics of a new nanoscale MOSFET concept is investigated through Quantum simulations. ► The RT-FET is a MOSFET with additional gate controlled tunnel barriers. ► RT-FETs have a lower RT-limited off-current and a high thermionic on-current. ► RT-FETs can achieve improved slope and Ion/Ioff ratios over conventional MOSFETs. ► RT-FETs can have slope below the kT/q limit and are immune to SD tunneling.
| | | | 12. | Simulation of the electrostatic and transport properties of 3D-stacked GAA silicon nanowire FETs Original Research Article
Pages 62-67
F.G. Ruiz, I.M. Tienda-Luna, A. Godoy, C. Sampedro, F. Gámiz, L. Donetti
Research highlights► We studied the electrostatic and transport properties of stacked nanowires (SNWs). ► We compared SNWs to a reference trigate transistor with similar dimensions. ► The calculated Nt in stacked NWs and trigates depends on the overall perimeter of the devices. ► The phonon-limited mobility shows a strong dependence on the WSi/HSi ratio. ► The electron mobility of stacked NWs depends on the biaxial strain induced during the fabrication process.
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