ScienceDirect Alert: Solid-State Electronics, Vol. 54, Iss. 9, 2010

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Solid-State Electronics Volume 54, Issue 9,  Pages 809-1050 (September 2010) Selected Papers from the ESSDERC 2009 Conference Edited by Athanasios Dimoulas and Dimitris Tsoukalas

1.

Editorial Board Page IFC

Editorial

2.

Foreward Page 809 A. Dimoulas, D. Tsoukalas

Regular Papers

3.

Scaling beyond CMOS: Turing-Heisenberg Rapprochement Pages 810-817 Victor V. Zhirnov, Ralph K. Cavin III

4.

Ultra-thin chip technology and applications, a new paradigm in silicon technology Pages 818-829 Joachim N. Burghartz, Wolfgang Appel, Christine Harendt, Horst Rempp, Harald Richter, Martin Zimmermann

5.

Function by defects at the atomic scale – New concepts for non-volatile memories Pages 830-840 Rainer Waser, Regina Dittmann, Martin Salinga, Matthias Wuttig

6.

Performance, reliability, radiation effects, and aging issues in microelectronics – From atomic-scale physics to engineering-level modeling Pages 841-848 Sokrates T. Pantelides, L. Tsetseris, M.J. Beck, S.N. Rashkeev, G. Hadjisavvas, I.G. Batyrev, B.R. Tuttle, A.G. Marinopoulos, X.J. Zhou, D.M. Fleetwood, R.D. Schrimpf

7.

Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and below Pages 849-854 C. Fenouillet-Beranger, P. Perreau, S. Denorme, L. Tosti, F. Andrieu, O. Weber, S. Monfray, S. Barnola, C. Arvet, Y. Campidelli, S. Haendler, R. Beneyton, C. Perrot, C. de Buttet, P. Gros, L. Pham-Nguyen, F. Leverd, P. Gouraud, F. Abbate, F. Baron, A. Torres, C. Laviron, L. Pinzelli, J. Vetier, C. Borowiak, A. Margain, D. Delprat, F. Boedt, K. Bourdelle, B.-Y. Nguyen, O. Faynot, T. Skotnicki

8.

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession Pages 855-860 T. Chiarella, L. Witters, A. Mercha, C. Kerner, M. Rakowski, C. Ortolland, L.-Å. Ragnarsson, B. Parvais, A. De Keersgieter, S. Kubicek, A. Redolfi, C. Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, T. Hoffmann

9.

Electrical and diffraction characterization of short and narrow MOSFETs on fully depleted strained silicon-on-insulator (sSOI) Pages 861-869 S. Baudot, F. Andrieu, O. Faynot, J. Eymery

10.

Ultra-high aspect-ratio FinFET technology Pages 870-876 Vladimir Jovanović, Tomislav Suligoj, Mirko Poljak, Yann Civale, Lis K. Nanver

11.

Small-signal analysis of high-performance p- and n-type SOI SB-MOSFETs with dopant segregation Pages 877-882 C. Urban, M. Emam, C. Sandow, Q.T. Zhao, A. Fox, S. Mantl, J.-P. Raskin

12.

Gate-all-around technology: Taking advantage of ballistic transport? Pages 883-889 J.L. Huguenin, G. Bidal, S. Denorme, D. Fleury, N. Loubet, A. Pouydebasque, P. Perreau, F. Leverd, S. Barnola, R. Beneyton, B. Orlando, P. Gouraud, T. Salvetat, L. Clement, S. Monfray, G. Ghibaudo, F. Boeuf, T. Skotnicki

13.

C–V profiling of ultra-shallow junctions using step-like background profiles Pages 890-896 Miloš Popadić, Vladimir Milovanović, Cuiqin Xu, Francesco Sarubbi, Lis K. Nanver

14.

Managing annealing pattern effects in 45 nm low power CMOS technology Pages 897-902 P. Morin, F. Cacho, R. Beneyton, B. Dumont, A. Colin, H. Bono, A. Villaret, E. Josse, R. Bianchini

15.

Formation of silicon ultra shallow junction by non-melt excimer laser treatment Pages 903-908 A. Florakis, A. Papadimitriou, N. Chatzipanagiotis, N. Misra, C. Grigoropoulos, D. Tsoukalas

16.

VDD scalability of FinFET SRAMs: Robustness of different design options against LER-induced variations Pages 909-918 Emanuele Baravelli, Luca De Marchi, Nicolò Speciale

17.

Self-aligned inversion-channel In0.75Ga0.25As metal–oxide–semiconductor field-effect-transistors using UHV-Al2O3/Ga2O3(Gd2O3) and ALD-Al2O3 as gate dielectrics Pages 919-924 T.D. Lin, H.C. Chiu, P. Chang, Y.H. Chang, Y.D. Wu, M. Hong, J. Kwo

18.

Electrical characterization of Si nanowire field-effect transistors with semi gate-around structure suitable for integration Pages 925-928 Soshi Sato, Hideyuki Kamimura, Hideaki Arai, Kuniyuki Kakushima, Parhat Ahmet, Kenji Ohmori, Keisaku Yamada, Hiroshi Iwai

19.

A quasi-analytical model for nanowire FETs with arbitrary polygonal cross section Pages 929-934 L. De Michielis, L. Selmi, A.M. Ionescu

20.

Asymmetrically strained all-silicon multi-gate n-Tunnel FETs Pages 935-941 M. Najmzadeh, K. Boucart, W. Riess, A.M. Ionescu

21.

Investigation of the performance of strained-SiGe vertical IMOS-transistors Pages 942-949 Thanh Viet Dinh, Rainer Kraus, Christoph Jungemann

22.

Theoretical analysis of the vertical LOCOS DMOS transistor with process-induced stress enhancement Pages 950-956 S. Reggiani, M. Denison, E. Gnani, A. Gnudi, G. Baccarani, S. Pendharkar, R. Wise

23.

Single-transistor latch-up and large-signal reliability in SOI CMOS RF power transistors Pages 957-964 F. Carrara, C.D. Presti, A. Scuderi, G. Palmisano

24.

Effective passivation and high-performance metal–oxide–semiconductor devices using ultra-high-vacuum deposited high-κ dielectrics on Ge without interfacial layers Pages 965-971 L.K. Chu, R.L. Chu, T.D. Lin, W.C. Lee, C.A. Lin, M.L. Huang, Y.J. Lee, J. Kwo, M. Hong

25.

HfO2-based gate stacks transport mechanisms and parameter extraction Pages 972-978 J. Coignus, C. Leroux, R. Clerc, R. Truche, G. Ghibaudo, G. Reimbold, F. Boulanger

26.

SILC decay in La2O3 gate dielectrics grown on Ge substrates subjected to constant voltage stress Pages 979-984 M.S. Rahman, E.K. Evangelou, I.I. Androulidakis, A. Dimoulas, G. Mavrou, S. Galata

27.

A novel self-refreshable capacitorless DRAM cell and its extended applications Pages 985-990 Peng-Fei Wang, Lei Liu, Dongping Wu, Song-Gan Zang, Wei Liu, Yi Gong, David Wei Zhang, Shi-Li Zhang

28.

Estimation of amorphous fraction in multilevel phase-change memory cells Pages 991-996 N. Papandreou, A. Pantazi, A. Sebastian, E. Eleftheriou, M. Breitwisch, C. Lam, H. Pozidis

29.

Modeling of gate-all-around charge trapping SONOS memory cells Pages 997-1002 E. Gnani, S. Reggiani, A. Gnudi, G. Baccarani, J. Fu, N. Singh, G.Q. Lo, D.L. Kwong

30.

Double-gate pentacene thin-film transistor with improved control in sub-threshold region Pages 1003-1009 Dimitrios Tsamados, Nenad V. Cvetkovic, Katrin Sidler, Jyotshna Bhandari, Veronica Savu, Juergen Brugger, Adrian M. Ionescu

31.

Epitaxial graphene field-effect transistors on silicon substrates Pages 1010-1014 Hyun-Chul Kang, Hiromi Karasawa, Yu Miyamoto, Hiroyuki Handa, Tetsuya Suemitsu, Maki Suemitsu, Taiichi Otsuji

32.

Simple and efficient modeling of the E–k relationship and low-field mobility in Graphene Nano-Ribbons Pages 1015-1021 Marco Bresciani, Pierpaolo Palestri, David Esseni, Luca Selmi

33.

Magneto-modulation of gate leakage current in 65 nm nMOS transistors: Experimental, modeling, and simulation results Pages 1022-1026 E.A. Gutierrez-D, J. Molina-R, P. Garcia-R, J. Martinez-C, F. Guarin

34.

On-chip Extraordinary Hall-effect sensors for characterization of nanomagnetic logic devices Pages 1027-1032 M. Becherer, J. Kiermaier, S. Breitkreutz, G. Csaba, X. Ju, J. Rezgani, T. Kießling, C. Yilmaz, P. Osswald, P. Lugli, D. Schmitt-Landsiedel

35.

Tunable band-stop filter based on single RF MEMS capacitive shunt switch with meander arm inductance Pages 1033-1040 Montserrat Fernández-Bolaños, Catherine Dehollain, Pierre Nicole, Adrian M. Ionescu

36.

Solidly mounted BAW resonators with layer-transferred AlN using sacrificial Si surfaces Pages 1041-1046 Mohamed Abd Allah, Robert Thalhammer, Jyrki Kaitila, Thomas Herzog, Werner Weber, Doris Schmitt-Landsiedel

37.

Electron magnetoresistance mobility in silicon-on-insulator layers using Kelvin’s technique Pages 1047-1050 J. Antoszewski, J.M. Dell, L. Faraone, N. Bresson, S. Cristoloveanu

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