ScienceDirect Alert: Solid-State Electronics, Vol. 54, Iss. 2, 2010

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Solid-State Electronics Volume 54, Issue 2,  Pages 85-220 (February 2010) Selected Full-Length Extended Papers from the EUROSOI 2009 Conference Edited by Olof Engström

1.

Editorial Board Page IFC

Editorial

2.

Foreword Page 85 Olof Engström

Regular Papers

3.

SOI versus bulk-silicon nanoscale FinFETs Pages 86-89 Jerry G. Fossum, Zhenming Zhou, Leo Mathew, Bich-Yen Nguyen

4.

Thin-film devices for low power applications Pages 90-96 S. Monfray, C. Fenouillet-Beranger, G. Bidal, F. Boeuf, S. Denorme, J.L. Huguenin, M.P. Samson, N. Loubet, J.M. Hartmann, Y. Campidelli, V. Destefanis, C. Arvet, K. Benotmane, L. Clement, O. Faynot, T. Skotnicki

5.

Performance estimation of junctionless multigate transistors Pages 97-103 Chi-Woo Lee, Isabelle Ferain, Aryan Afzalian, Ran Yan, Nima Dehdashti Akhavan, Pedram Razavi, Jean-Pierre Colinge

6.

Dynamic body potential variation in FD SOI MOSFETs operated in deep non-equilibrium regime: Model and applications Pages 104-114 M. Bawedin, S. Cristoloveanu, D. Flandre, F. Udrea

7.

Suppression of gate-induced drain leakage by optimization of junction profiles in 22 nm and 32 nm SOI nFETs Pages 115-122 Andreas Schenk

8.

Mobility enhancement by CESL strain in short-channel ultrathin SOI MOSFETs Pages 123-130 L. Pham-Nguyen, C. Fenouillet-Beranger, G. Ghibaudo, T. Skotnicki, S. Cristoloveanu

9.

Multi-Subband Monte Carlo study of device orientation effects in ultra-short channel DGSOI Pages 131-136 C. Sampedro, F. Gámiz, A. Godoy, R. Valín, A. García-Loureiro, F.G. Ruiz

10.

Electron subband structure in strained silicon UTB films from the Hensel–Hasegawa–Nakayama model – Part 1 analytical consideration and strain-induced valley splitting Pages 137-142 Thomas Windbacher, Viktor Sverdlov, Oskar Baumgartner, Siegfried Selberherr

11.

Electron subband structure in strained silicon UTB films from the Hensel–Hasegawa–Nakayama model – Part 2 efficient self-consistent numerical solution of the k · p schrödinger equation Pages 143-148 Oskar Baumgartner, Markus Karner, Viktor Sverdlov, Hans Kosina

12.

Physical modeling of millimetre wave signal reflection from forward biased PIN diodes Pages 149-152 R.P. Jackson, S.J.N. Mitchell, V. Fusco

13.

Oxygen out-diffusion from buried layers in SOI and SiC–SOI substrates Pages 153-157 L.-G. Li, Ö. Vallin, J. Lu, U. Smith, H. Norström, J. Olsson

14.

Fabrication of Silicon on Diamond (SOD) substrates by either the Bonded and Etched-back SOI (BESOI) or the Smart-Cut™ technology Pages 158-163 J. Widiez, M. Rabarot, S. Saada, J.-P. Mazellier, J. Dechamp, V. Delaye, J.-C. Roussin, F. Andrieu, O. Faynot, S. Deleonibus, P. Bergonzo, L. Clavelier

15.

Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxides Pages 164-170 T. Rudenko, V. Kilchytska, S. Burignat, J.-P. Raskin, F. Andrieu, O. Faynot, Y. Le Tiec, K. Landry, A. Nazarov, V.S. Lysenko, D. Flandre

16.

Large-signal analysis of substrate effects in RF-power SOI-LDMOS transistors Pages 171-177 Lars Vestling, Olof Bengtsson, Klas-Håkan Eklund, Jörgen Olsson

17.

Effect of rotation, gate-dielectric and SEG on the noise behavior of advanced SOI MuGFETs Pages 178-184 S. Put, H. Mehta, N. Collaert, M. Van Uffelen, P. Leroux, C. Claeys, N. Lukyanchikova, E. Simoen

18.

Systematic study of Schottky barrier MOSFETs with dopant segregation on thin-body SOI Pages 185-190 C. Urban, C. Sandow, Q.-T. Zhao, J. Knoch, S. Lenk, S. Mantl

19.

Hole transport in DGSOI devices: Orientation and silicon thickness effects Pages 191-195 L. Donetti, F. Gámiz, N. Rodrı´guez, F. Jiménez-Molinos, J.B. Roldán

20.

Effect of high-energy neutrons on MuGFETs Pages 196-204 V. Kilchytska, J. Alvarado, N. Collaert, R. Rooyakers, O. Militaru, G. Berger, D. Flandre

21.

Low-temperature characterization and modeling of advanced GeOI pMOSFETs: Mobility mechanisms and origin of the parasitic conduction Pages 205-212 W. Van Den Daele, E. Augendre, C. Le Royer, J.-F. Damlencourt, B. Grandchamp, S. Cristoloveanu

22.

Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel Pages 213-219 S. Burignat, D. Flandre, M.K. Md Arshad, V. Kilchytska, F. Andrieu, O. Faynot, J.-P. Raskin

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