ScienceDirect Alert: Solid-State Electronics, Vol. 52, Iss. 12, 2008

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Solid-State Electronics Volume 52, Issue 12,  Pages 1839-1946 (December 2008) Selected Papers from the EUROSOI '08 Conference Edited by Dimitri Lederer and Jean-Pierre Colinge

1.

Editorial Board Page IFC

Editorial

2.

Foreword Page 1839 Dimitri Lederer, Jean-Pierre Colinge

Regular Papers

3.

Germanium on sapphire by wafer bonding Pages 1840-1844 P.T. Baine, H.S. Gamble, B.M. Armstrong, D.W. McNeill, S.J.N. Mitchell, Y.H. Low, P.V. Rainey

4.

Evaluation of super-critical thickness strained-Si on insulator (sc-SSOI) substrate Pages 1845-1848 A. Ogura, T. Yoshida, D. Kosemura, Y. Kakemura, M. Takei, H. Saito, T. Shimura, T. Koganesawa, I. Hirosawa

5.

Fabrication and characterisation of high resistivity SOI substrates for monolithic high energy physics detectors Pages 1849-1853 F.H. Ruddell, S.L. Suder, M.F. Bain, J.H. Montgomery, B.M. Armstrong, H.S. Gamble, D. Denvir, G. Casse, T. Bowcock, P.P. Allport, J. Marczewski, K. Kucharski, D. Tomaszewski, H. Niemiec, W. Kucewicz

6.

Modeling the equivalent oxide thickness of Surrounding Gate SOI devices with high-κ insulators Pages 1854-1860 I.M. Tienda-Luna, F.J. García Ruiz, L. Donetti, A. Godoy, F. Gámiz

7.

Electron subband structure and controlled valley splitting in silicon thin-body SOI FETs: Two-band k · p theory and beyond Pages 1861-1866 Viktor Sverdlov, Siegfried Selberherr

8.

Compact charge and capacitance modeling of undoped ultra-thin body (UTB) SOI MOSFETs Pages 1867-1871 Oana Moldovan, Ferney A. Chaves, David Jiménez, Benjamin Iñiguez

9.

Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations Pages 1872-1876 Ran Yan, Danny Lynch, Thibault Cayron, Dimitri Lederer, Aryan Afzalian, Chi-Woo Lee, Nima Dehdashti, J.P. Colinge

10.

Threshold voltages of SOI MuGFETs Pages 1877-1883 Maria Glória Caño de Andrade, João Antonio Martino

11.

Analysis of STI-induced mechanical stress-related Kink effect of 40 nm PD SOI NMOS devices biased in saturation region Pages 1884-1888 I.S. Lin, V.C. Su, J.B. Kuo, D. Chen, C.S. Yeh, C.T. Tsai, M. Ma

12.

Impact of strain and source/drain engineering on the low frequency noise behaviour in n-channel tri-gate FinFETs Pages 1889-1894 W. Guo, B. Cretu, J.-M. Routoure, R. Carin, E. Simoen, A. Mercha, N. Collaert, S. Put, C. Claeys

13.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications? Pages 1895-1903 Abhinav Kranti, G. Alastair Armstrong

14.

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs Pages 1904-1909 Marcelo Antonio Pavanello, Joao Antonio Martino, Eddy Simoen, Rita Rooyackers, Nadine Collaert, Cor Claeys

15.

Substrate bias and operating temperature effects on the performance of Schottky-barrier SOI nMOSFETs Pages 1910-1914 Dae Hyun Ka, Jin-Wook Shin, Won-Ju Cho, Jong Tae Park

16.

Temperature behavior of spiral inductors on high resistivity substrate in SOI CMOS technology Pages 1915-1923 M. El Kaamouchi, P. Delatte, M. Si Moussa, J.-P. Raskin, D. Vanhoenacker-Janvier

17.

High-temperature DC and RF behaviors of partially-depleted SOI MOSFET transistors Pages 1924-1932 Mostafa Emam, Julio C. Tinoco, Danielle Vanhoenacker-Janvier, Jean-Pierre Raskin

18.

Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer Pages 1933-1938 Michelly de Souza, Denis Flandre, Marcelo Antonio Pavanello

19.

Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology Pages 1939-1945 David Bol, Julien De Vos, Renaud Ambroise, Denis Flandre, Jean-Didier Legat

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