ScienceDirect Alert: Solid-State Electronics, Vol. 52, Iss. 9, 2008

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Solid-State Electronics Volume 52, Issue 9,  Pages 1265-1472 (September 2008) Papers Selected from the 37th European Solid-State Device Research Conference - ESSDERC’07 Edited by Jurriaan Schmitz and Roland Thewes

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Editorial Board Page IFC

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Special issue devoted to the ESSDERC’07 conference Page 1265 Jurriaan Schmitz and Roland Thewes

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45 nm/32 nm CMOS – Challenge and perspective Pages 1266-1273 Kazunari Ishimaru

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High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy Pages 1274-1279 B. Raeissi, J. Piscator, O. Engström, S. Hall, O. Buiu, M.C. Lemme, H.D.B. Gottlob, P.K. Hurley, K. Cherkaoui and H.J. Osten

5.

Origin of flat band voltage shift in HfO2 gate dielectric with La2O3 insertion Pages 1280-1284 K. Kakushima, K. Okamoto, M. Adachi, K. Tachi, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori and H. Iwai

6.

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers Pages 1285-1290 C. Le Royer, L. Clavelier, C. Tabone, K. Romanjek, C. Deguet, L. Sanchez, J.-M. Hartmann, M.-C. Roure, H. Grampeix, S. Soliveres, G. Le Carval, R. Truche, A. Pouydebasque, M. Vinet and S. Deleonibus

7.

Multi-gate devices for the 32 nm technology node and beyond Pages 1291-1296 N. Collaert, A. De Keersgieter, A. Dixit, I. Ferain, L.-S. Lai, D. Lenoble, A. Mercha, A. Nackaerts, B.J. Pawlak, R. Rooyackers, T. Schulz, K.T. San, N.J. Son, M.J.H. Van Dal, P. Verheyen, K. von Arnim, L. Witters, K. De Meyer, S. Biesemans and M. Jurczak

8.

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI Pages 1297-1302 Emilie Bernard, T. Ernst, B. Guillaumot, N. Vulliet, X. Garros, V. Maffini-Alvaro, P. Coronel, T. Skotnicki and S. Deleonibus

9.

Achieving low-VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack Pages 1303-1311 A. Veloso, H.Y. Yu, A. Lauwers, S.Z. Chang, C. Adelmann, B. Onsia, M. Demand, S. Brus, C. Vrancken, R. Singanamalla, P. Lehnen, J. Kittl, T. Kauerauf, R. Vos, B.J. O′Sullivan, S. Van Elshocht, R. Mitsuhashi, G. Whittemore, K.M. Yin, M. Niwa, T. Hoffmann, P. Absil, M. Jurczak and S. Biesemans

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Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach Pages 1312-1317 K.D. Buddharaju, N. Singh, S.C. Rustagi, Selin H.G. Teo, G.Q. Lo, N. Balasubramanian and D.L. Kwong

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A new definition of threshold voltage in Tunnel FETs Pages 1318-1323 Kathy Boucart and Adrian Mihai Ionescu

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Examination of the high-frequency capability of carbon nanotube FETs Pages 1324-1328 David L. Pulfrey and Li Chen

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Phonon-scattering effects in CNT-FETs with different dimensions and dielectric materials Pages 1329-1335 Roberto Grassi, Stefano Poli, Susanna Reggiani, Elena Gnani, Antonio Gnudi and Giorgio Baccarani

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Punch-through impact ionization MOSFET (PIMOS): From device principle to applications Pages 1336-1344 K.E. Moselund, D. Bouvet, V. Pott, C. Meinen, M. Kayal and A.M. Ionescu

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Single-grain Si thin-film transistors SPICE model, analog and RF circuit applications Pages 1345-1352 A. Baiano, M. Danesh, N. Saputra, R. Ishihara, J. Long, W. Metselaar, C.I.M. Beenakker, N. Karaki, Y. Hiroshima and S. Inoue

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Investigation and improvement of DMOS switches under fast electro-thermal cycle stress Pages 1353-1358 Tobias Smorodin, Peter Nelle, Jörg Busch, Jürgen Wilde, Michael Glavanovics and Matthias Stecher

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Aluminum nitride for heatspreading in RF IC’s Pages 1359-1363 L. La Spina, E. Iborra, H. Schellevis, M. Clement, J. Olivares and L.K. Nanver

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Joining microelectronics and microionics: Nerve cells and brain tissue on semiconductor chips Pages 1364-1373 Peter Fromherz

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Finite element analysis and analytical simulations of Suspended Gate-FET for ultra-low power inverters Pages 1374-1381 Dimitrios Tsamados, Yogesh Singh Chauhan, Christoph Eggimann, Kerem Akarvardar, H.-S. Philip Wong and Adrian Mihai Ionescu

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Anodic Ta2O5 for CMOS compatible low voltage electrowetting-on-dielectric device fabrication Pages 1382-1387 Y. Li, W. Parkes, L.I. Haworth, A.A. Stokes, K.R. Muir, P. Li, A.J. Collin, N.G. Hutcheon, R. Henderson, B. Rae and A.J. Walton

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Electrothermal noise analysis in frequency tuning of nanoresonators Pages 1388-1393 Seong Chan Jun, Hyungbin Son, C.W. Baik, J.M. Kim, S.W. Moon, H. Jin Kim, X.M.H. Huang and J. Hone

22.

Nano-gap micro-electro-mechanical bulk lateral resonators with high quality factors and low motional resistances on thin silicon-on-insulator Pages 1394-1400 N.D. Badila-Ciressan, M. Mazza, D. Grogg and A.M. Ionescu

23.

CMOS image sensors: State-of-the-art Pages 1401-1406 Albert J.P. Theuwissen

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Degradation of CMOS image sensors in deep-submicron technology due to γ-irradiation Pages 1407-1413 Padmakumar R. Rao, Xinyang Wang and Albert J.P. Theuwissen

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The Monte Carlo approach to transport modeling in deca-nanometer MOSFETs Pages 1414-1423 Enrico Sangiorgi, Pierpaolo Palestri, David Esseni, Claudio Fiegna and Luca Selmi

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On a computationally efficient approach to boron-interstitial clustering Pages 1424-1429 J. Schermer, A. Martinez-Limia, P. Pichler, C. Zechner, W. Lerch and S. Paul

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From point defects to dislocation loops: A comprehensive modelling framework for self-interstitial defects in silicon Pages 1430-1436 Ignacio Martin-Bragado, Ibrahim Avci, Nikolas Zographos, Martin Jaraiz and Pedro Castrillo

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Microscopic modeling of hole inversion layer mobility in unstrained and uniaxially stressed Si on arbitrarily oriented substrates Pages 1437-1442 A.T. Pham, C. Jungemann and B. Meinerzhagen

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Status and challenges of phase change memory modeling Pages 1443-1451 A.L. Lacaita, D. Ielmini and D. Mantegazza

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Integration of CVD silicon nanocrystals in a 32 Mb NOR flash memory Pages 1452-1459 S. Jacob, B. De Salvo, L. Perniola, G. Festes, S. Bodnar, R. Coppard, J.F. Thiery, T. Pate-Cazal, C. Bongiorno, S. Lombardo, J. Dufourcq, E. Jalaguier, T. Pedron, F. Boulanger and S. Deleonibus

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Long term charge retention dynamics of SONOS cells Pages 1460-1466 A. Arreghini, N. Akil, F. Driussi, D. Esseni, L. Selmi and M.J. van Duuren

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Phase-change memory technology with self-aligned μTrench cell architecture for 90 nm node and beyond Pages 1467-1472 A. Pirovano, F. Pellizzer, I. Tortorelli, A. Riganó, R. Harrigan, M. Magistretti, P. Petruzza, E. Varesi, A. Redaelli, D. Erbetta, T. Marangon, F. Bedeschi, R. Fackenthal, G. Atwood and R. Bez

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