---------------
*******************************************
Analog and Mixed Mode Circuits and Systems
*******************************************
CMOS High-CMRR Current Output Stages
Centurelli, F.; Grasso, A. D.; Pennisi, S.; Scotti, G.; Trifiletti, A.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303315.pdf?isnumber=4303314
Two CMOS current output stages are presented. Compared to the
traditional solution, which exhibits unbalanced operation, the proposed
ones exploit an auxiliary high-gain feedback loop which provides
differential drive, thereby highly improving the common-mode rejection
ratio (CMRR). Prototypes are designed and fabricated in a 0.35-$mu{hbox
{m}}$ technology and experimental results confirm that a CMRR increase
greater than 20 dB can be achieved and, for one of the two solutions,
without increasing the voltage requirements.
-------
A Wide Locking-Range Frequency Divider for LMDS Applications
Lin, H.-Y.; Hsu, S. S. H.; Chan, C.-Y.; Jin, J.-D.; Lin, Y.-S.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303325.pdf?isnumber=4303314
A fully integrated frequency divider with an operation frequency up to
20 GHz is designed in 0.18-$mu{hbox {m}}$ CMOS technology. The frequency
divider includes two stages to divide the input signal by a factor of 4.
A wide locking range from 18.8 to 23.2 GHz was obtained with a low phase
noise of ${- 134.8}~{hbox {dBc/Hz}}$ (1-MHz offset) at an output
frequency of 4.7 GHz. The first stage is designed by an analog
methodology with the varactors to extend the locking range, while the
second stage is designed by a digital approach with the RF devices for a
high operation frequency. With the advantages of both designs, this
frequency divider is operated at the frequency range suitable for LMDS
applications.
-------
A High Slew-Rate Push-Pull Output Amplifier for Low-Quiescent Current
Low-Dropout Regulators With Transient-Response Improvement
Man, T. Y.; Mok, P. K. T.; Chan, M.
..
http://ieeexplore.ieee.org/iel5/8920/4303314/04303328.pdf?isnumber=4303314
A high slew-rate amplifier with push-pull output driving capability is
proposed to enable an ultra-low quiescent current ( ${I}_{Q} sim
1~mu{hbox {A}}$) low-dropout (LDO) regulator with improved transient
responses. The proposed amplifier eliminates the tradeoff between small
${I}_{Q}$ and large slew-rate that is imposed by the tail-current in
conventional amplifier design. Push-pull output stage is introduced to
enhance the output driving ability. Small dropout voltage (${V}_{rm
DO}$) with large-size pass transistor and ultra-low ${I}_{Q}$ can thus
be used to minimize power loss of LDO regulator without
transient-response degradation. The proposed amplifier helps to improve
stability of LDO regulators without using any on-chip and off-chip
compensation capacitors. This is beneficial to chip-level power
management requiring high-area efficiency. An LDO regulator with the
proposed amplifier has been implemented in a 0.18-$mu{hbox {m}}$
standard CMOS process and occupies 0.09 ${hbox {mm}}^{2}$. The LDO
regulator can deliver 50-mA load current at 1-V input and $sim 100{hbox
{-mV} }~{V}_{rm DO}$. It only consumes 1.2 $mu{hbox {A}}~{I}_{Q}$ and is
able to recover within $sim 4~mu{hbox {s}}$ even under the worst case
scenario.
-------
The Stochastic I-Pot: A Circuit Block for Programming Bias Currents
Serrano-Gotarredona, R.; Camunas-Mesa, L.; Serrano-Gotarredona, T.;
Lenero-Bardallo, J. A.; Linares-Barranco, B.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303336.pdf?isnumber=4303314
In this brief, we present the "Stochastic I-Pot." It is a circuit
element that allows for digitally programming a precise bias current
ranging over many decades, from pico-amperes up to hundreds of
micro-amperes. I-Pot blocks can be chained within a chip to allow for
any arbitrary number of programmable bias currents. The approach only
requires to provide the chip with three external pins, the use of an
external current measuring instrument, and a computer. This way, once
all internal I-Pots have been characterized, they can be programmed
through a computer to provide any desired current bias value with very
low error. The circuit block turns out to be very practical for
experimenting with new circuits (specially when a large number of biases
are required), testing wide ranges of biases, introducing means for
current mismatch calibration, offsets compensations, etc. using a
reduced number of chip pins. We show experimental results of generating
bias currents with errors of 0.38% (8 bits) for currents varying from
176 $mu{hbox {A}}$ to 19.6 pA. Temperature effects are characterized.
------
*************************************
Digital Circuits and Systems and VLSI
*************************************
An ARM-Based System-on-a-Programmable-Chip Architecture for Spoken
Language Translation
Lin, S.-C.; Wang, J.-C.; Wang, J.-F.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303326.pdf?isnumber=4303314
Previous research shows that there are two architectures for spoken
language translation (SLT) system implementation. One is client-server
based systems that should be built on the server computer but
unreliability of the remote connection. The other is to build portable
stand-alone devices but it lacks real-time performance. In this brief, a
system-on-a-programmable-chip (SoPC) solution is proposed by realizing
the entire SLT system within a single chip. This SoPC is characterized
by small size, low cost, real-time operation, and high portability. This
entire design was implemented on ALTERA EPXA10 device. Performance for
English-to-Mandarin translation process can be completed within 1 s at a
46.22-MHz clock frequency with 3000 translation patterns. The total
logic usage of the EPXA10 device is 50% (about 19318 logic cells).
-------
Multiplierless, Folded 9/7- 5/3 Wavelet VLSI Architecture
Martina, M.; Masera, G.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303329.pdf?isnumber=4303314
This brief proposes a multiplierless VLSI architecture for the famous
9/7 wavelet filters. The novelty of this architecture is the possibility
to compute the 5/3 wavelet results into the 9/7 data path with a reduced
number of adders compared to other solutions. The multiplierless
architecture has been characterized in terms of performance through
simulations into a JPEG2000 environment and compared to other solutions.
Implementation on a 0.13-$mu{hbox {m}}$ standard cell technology shows
that the proposed architecture compared to other multiplierless
architectures requires a reduced amount of logic with excellent performance.
-------
RNS-To-Binary Converter for a New Three-Moduli Set
${2^{{n}+1}-1,2^{n},2^{n}-1}$
Mohan, P. V. A.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303330.pdf?isnumber=4303314
In this brief, the design of residue number system (RNS) to binary
converters for a new powers-of-two related three-moduli set
${2^{{n}+1}-1,2^{n},2^{n}-1}$ is considered. This moduli set uses moduli
of uniform word length (n to ${n}+1 {rm bits}$). It is derived from a
previously investigated four-moduli set
${2^{n}-1,2^{n},2^{n}+1,2^{{n}+1}-1}$ . Three RNS-to-binary converters
are proposed for this moduli set: one using mixed radix conversion and
the other two using Chinese Remainder Theorem. Detailed architectures of
the three converters as well as comparison with some earlier proposed
converters for three-moduli sets with uniform word length and the
four-moduli set ${2^{n}-1,2^{n},2^{n}+1,2^{{n}+1}-1}$ are presented.
-------
*****************
Signal Processing
******************
Optimal Use of Some Classical Approximations in Filter Design
Dimopoulos, H. G.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303320.pdf?isnumber=4303314
The classical Butterworth, Chebyshev and Elliptic (Cauer) low-pass
filter approximations can be used in the design of analog and IIR
digital filters in such a way as to obtain passband, stopband and
transition band optimized filters at no order cost. The exact analytical
relationships for such an optimal deployment of these approximations are
developed and presented in this paper and their use is demonstrated
through design examples.
-------
A Complex Variable Fractional-Delay FIR Filter Structure
Hermanowicz, E.; Johansson, H.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303323.pdf?isnumber=4303314
This brief introduces a structure for complex variable fractional delay
(FD) finite-length impulse response (FIR) filters. The structure is
derived from a real variable FD FIR filter and is constituted by a set
of fixed real linear-phase FIR filters and two multiply-accumulate
chains containing variable multipliers. In this way the implementation
complexity and delay may be reduced in comparison with the cascade
approach which hitherto has been used for the same purpose. A design
example is included to demonstrate the benefits of the new structure.
-------
Polyphase Conditions and Structures for 2-D Quincunx FIR Filter Banks
Having Quadrantal or Diagonal Symmetries
Patwardhan, P. G.; Patil, B.; Gadre, V. M.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303334.pdf?isnumber=4303314
In this brief, we derive conditions on the polyphase matrix of 2-D
finite-impulse response (FIR) quincunx filter banks, for the filters in
the filter bank to have quadrantal or diagonal symmetry. These
conditions provide a framework for synthesizing polyphase structures
which structurally enforce the symmetry. This is demonstrated by
constructing examples of small parameterized matrix structures which
satisfy the above conditions, thus giving perfect reconstruction FIR
quincunx filter banks with quadrantal or diagonally symmetric
short-kernel (i.e., short-support) filters. It is also shown that
cascades of the above constructed small structures can be used to
construct filters of higher order.
-------
******************************
Nonlinear Circuits and Systems
******************************
More on Security of Public-Key Cryptosystems Based on Chebyshev Polynomials
Cheong, K. Y.; Koshiba, T.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303316.pdf?isnumber=4303314
Recently, a public-key cryptosystem based on Chebyshev polynomials has
been proposed, but it has been later analyzed and shown insecure. This
paper addresses some unanswered questions about the cryptosystem. We
deal with the issue of computational precision. This is important for
two reasons. Firstly, the cryptosystem is defined on real numbers, but
any practical data communication channel can only transmit a limited
number of digits. Any real number can only be specified to some
precision level, and we study the effect of that. Secondly, we show that
the precision issue is related to its security. In particular, the
algorithm previously proposed to break the cryptosystem may not work in
some situations. Moreover, we introduce another method to break the
cryptosystem with general precision settings. We extend the method to
show that a certain class of cryptosystems is insecure. Our method is
based on the known techniques on the shortest vector problem in lattice
and linear congruences.
-------
Remarks on Analysis, Design and Amplitude Stability of MOS Colpitts
Oscillator
Filanovsky, I. M.; Verhoeven, C. J. M.; Reja, M.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303321.pdf?isnumber=4303314
The small-signal analysis shows that the MOS Colpitts oscillator is
described by a third order characteristic equation. The procedure for
finding the second order approximation is defined, and the solution
corresponding to this approximation is found. Then the equations for
transistor transconductance describing function are analyzed, and the
design procedure corresponding to the "convenient" operation point is
given. The same equations are also used for the analysis of amplitude
stability in this oscillator. It is shown that the amplitude
self-modulation (squegging) in the considered oscillator is absent for
any conducting angle of the transistor.
-------
Control of Fast Scale Bifurcations in Power-Factor Correction Converters
Giaouris, D.; Banerjee, S.; Zahawi, B.; Pickert, V.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303322.pdf?isnumber=4303314
This brief proposes a novel controller which greatly enhances the
performance of a power-factor correction converter. This controller is
optimally tuned to place the eigenvalues of the system well inside the
unit circle and hence it guarantees stable operation over a wide range
of input voltages. The design of the controller is based on the
stability analysis of the system using the state transition matrix over
a clock cycle. It is shown that the transition matrix across the
switching manifold greatly influences the system's performance, allowing
the system to be stabilized by periodically altering the manifold. The
results are validated by analytical and numerical studies.
------
Active $Q$-Factor and Equilibrium Stability Formulation for Sinusoidal
Oscillators
Ohira, T. O.; Araki, K.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303333.pdf?isnumber=4303314
Quality factor ($Q$ -factor) and stability criterion of sinusoidal
oscillators are formulated from the viewpoints of energy equilibrium and
spectrum purity. Complex power works as an objective function to
determine the steady-state oscillation amplitude and frequency.
Conjugate product of amplitude and frequency slopes of the function
dominates equilibrium stability. Logarithmic derivative of oscillator's
output impedance defines active $Q$ -factor, which takes into account
effects of positive power generated by active devices, while keeping its
non-divergent property. Transfer $Q$-factor is also defined for
oscillating networks involving noise sources on different branches from
the port of spectrum observation. Presented formulas can be applied to
the entire oscillator circuit without de-embedding active devices, and
thus they enable frequency-domain CAD simulators to numerically evaluate
oscillator performance.
------
*************************************
Control Theory and Systems
*************************************
IP Observer Design for Descriptor Linear Systems
Wu, A.-G.; Duan, G.-R.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303337.pdf?isnumber=4303314
The new type of integral proportional (IP) observers for descriptor
linear systems is proposed. Based on a parametric solution to a type of
matrix equations, a parametric approach for the design of the IP
observers is established. The proposed approach guarantees the
regularity of the observer systems, and gives parameterizations of all
observer gains in terms of some free parameters.
------
*************************************
Circuits and Systems for Communications
*************************************
A Subsampling Quadrature $Sigma Delta$ Modulator Based on Distributed
Resonators for Use in Radio Receiver
Reekmans, S.; Hernandez, L.; Prefasi, E.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303335.pdf?isnumber=4303314
The receiver architecture proposed in this brief seizes the subsampling
properties of continuous-time sigma-delta ( $Sigma Delta$) modulators
based on distributed resonators to construct a quadrature receiver. The
proposed architecture is based on a low-pass $Sigma Delta$ modulator
that subsamples an intermediate frequency signal around the sampling
frequency and does not require quadrature mixers. Instead, the
quadrature mixing is replaced by suitably choosing the sampling instants
inside the loop. Two practical circuit implementations are proposed. The
first one uses separate circuitry for the $I$ and $Q$ paths. The second
architecture introduces an innovative way to produce the $I$ and $Q$
outputs that is immune to path mismatch due to the sharing of all the
analog circuitry for both paths. The proposed modulator may be feasible
for the typical IF frequencies used in cellular base stations.
-------
******************************************************
Power Systems and Electronic Circuits
******************************************************
Fast-Transient PCCM Switching Converter With Freewheel Switching Control
Ma, D.; Ki, W.-H.
http://ieeexplore.ieee.org/iel5/8920/4303314/04303327.pdf?isnumber=4303314
This brief presents a new switching converter operating in
pseudo-continuous-conduction mode (PCCM) with freewheel switching
control. Compared with conventional discontinuous-conduction mode (DCM)
converters, this converter demonstrates much improved current handling
capability with reduced current and voltage ripples. The
control-to-output transfer function exhibits a single-pole behavior,
making the load transient response much faster than its CCM
counterparts. Simulation and experimental results show that, with a 6-V,
6-W load and a 10-V unregulated supply, the PCCM converter has a current
ripple of only 1.1 A and a ripple voltage of only 58 mV, while a DCM
converter has a current ripple of 2.2 A and a ripple voltage of 220 mV.
In addition, the PCCM converter takes only 25 $mu{hbox {s}}$ to respond
to a 500-mA load current change while a CCM one requires 1.4 ms.
==================================================================
OCTOBER 2007 ISSUE
---------------
*******************************************
Analog and Mixed Mode Circuits and Systems
*******************************************
Modeling and Design of CMOS UHF Voltage Multiplier for RFID in an EEPROM
Compatible Process
Bergeret, E.; Gaubert, J.; Pannier, P.; Gaultier, J. M.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349219.pdf?isnumber=4349216
Modeling and design of CMOS ultra-high-frequency (UHF) voltage
multipliers are presented. These circuits recover power from incident
radio frequency (RF) signal and supply battery less UHF RF
identification (RFID) transponders. An analytical model of CMOS UHF
voltage multipliers is developed. It permits to determine the main
design parameters in order to improve multiplier performance. The design
of this kind of circuits is then greatly simplified and simulation time
is reduced. Thanks to this model, a voltage multiplier is designed and
implemented in a low-cost electrically erasable programmable read-only
memory compatible CMOS process without Schottky diodes layers.
Measurements results show communication ranges up to 5 m in the U.S.
standard.
-------
Advancing Data Weighted Averaging Technique for Multi-Bit Sigma-Delta
Modulators
Lee, D.-H.; Kuo, T.-H.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349226.pdf?isnumber=4349216
Multibit sigma-delta modulators which employ the data weighted averaging
(DWA) technique are plagued by baseband tone problems. The existing
DWA-like techniques for solving these problems are categorized in this
brief as tone-suppressing and tone-transferring techniques. Although
tone-transferring techniques can achieve a better
signal-to-noise-plus-distortion ratio than tone-suppressing techniques,
they may behave unfavorably for input signals with dc components. A
flexible DWA-like technique, designated as "advancing DWA" (ADWA), which
can achieve both tone-suppressing and tone-transferring functions, is
proposed. It can be configured as a tone-transferring technique by
advancing the starting selection of the element array by a fixed step
for the subsequent element selection cycle. Moreover, ADWA can also be
configured as a tone-suppressing technique to reduce tones by randomly
performing the advancing actions. Therefore, ADWA can be a
reconfigurable technique that uses configuration settings from
designers, or an auto-configurable technique that uses input signal
detection schemes to set its configuration.
-------
An Ultra-Low-Voltage Ultra-Low-Power CMOS Miller OTA With Rail-to-Rail
Input/Output Swing
Ferreira, L. H. C.; Pimenta, T. C.; Moreno, R. L.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349224.pdf?isnumber=4349216
An ultra-low-voltage ultra-low-power CMOS Miller operational
transconductance amplifier (OTA) with rail-to-rail input/output swing is
presented. The topology is based on combining bulk-driven differential
pair and dc level shifters, with the transistors work in weak inversion.
The improved Miller OTA has been successfully verified in a standard
0.35-$mu{hbox {m}}$ CMOS process. Experimental results have confirmed
that, at a minimum supply voltage of 600 mV, lower than the threshold
voltage, the topology presents almost rail-to-rail input and output
swings and consumes only 550 nW.
-------
Linearization Technique for Source-Degenerated CMOS Differential
Transconductors
Monsurro, P.; Pennisi, S.; Scotti, G.; Trifiletti, A.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349232.pdf?isnumber=4349216
A supplementary linearization technique for CMOS differential pairs with
resistive source degeneration is proposed. The approach exploits an
auxiliary (degenerated) differential pair to drive the bulk terminals of
the main pair. Transistor-level simulations on a design using a 0.25-
$mu{hbox {m}}$ process and powered with 2.5 V and 1 mA, show that total
harmonic distortion (THD) in the voltage-to-current conversion is
decreased by 10 dB (for an input differential signal with a peak
amplitude of 0.5 V and for frequencies up to 100 MHz) compared to the
traditional source-degenerated transconductor. This THD improvement is
achieved with a negligible increase in power consumption.
-------
A Model for Temperature Insensitive Trimmable MOSFET Current Sources
Shah, S.; Collins, S.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349238.pdf?isnumber=4349216
High-precision current-steering digital-analog converters (DACs) can
only be created by limiting variations between the outputs of individual
current sources within each DAC. One possible approach to limit these
variations is to create a trimmable circuit which includes a
floating-gate device acting as an analogue nonvolatile memory. Results
are presented which show that one type of trimmable current source has a
bias condition at which its output current is both trimmable and robust
to temperature variations. A model of this potentially useful behavior
is presented which suggests that it arises from a combination of the
temperature dependence of a MOSFET and the modulation of its source
voltage caused by a second MOSFET acting as a voltage controlled resistor.
-------
Measured CMOS Switched High-Quality Capacitors in a Reconfigurable
Matching Network
Sjoblom, P.; Sjoland, H.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349240.pdf?isnumber=4349216
Switched capacitors are here investigated for use in reconfigurable
matching networks, particularly for digital video broadcasting-handheld
(DVB-H) frequencies. A 0.13-$mu{hbox {m}}$ CMOS circuit is evaluated
through both simulations and measurements. Source grounded nMOS
transistors are used to switch high-quality metal capacitors located
above metal layer 8. The quality factor and tuning range depend on
frequency, switch voltage, capacitor size, and transistor width. There
is a clear tradeoff between quality factor and tuning range, and
measurements show quality factors above 50, 100, and 150 at tuning
ranges of 3.9, 2.4, and 1.6, respectively. A reconfigurable matching
network with the switched capacitors has been realized using external
inductors and the measured matching domain for the DVB-H frequency band
is shown. The total loss of the network is 1.0 dB, a result of the
high-quality switched capacitors.
-------
*************************************
Digital Circuits and Systems and VLSI
*************************************
High-Throughput VLSI Architecture for FFT Computation
Cheng, C.; Parhi, K. K.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349220.pdf?isnumber=4349216
In this brief, multi-path delay commutator structures are utilized to
improve the throughput rate of radix-2 and radix-4 FFT computation by a
factor of 2 to 4. Latency can also be reduced by a factor of 2 to 3.
Compared with previous radix-2 and radix-4 FFT structures, the proposed
high-throughput FFT with doubled throughput rate requires similar or
even less hardware cost. Although split radix FFT design is more
hardware efficient, the regular structure of proposed FFT structures are
attractive for high throughput FFT design.
-------
Validation of a Full-Chip Simulation Model for Supply Noise and Delay
Dependence on Average Voltage Drop With On-Chip Delay Measurement
Ogasahara, Y.; Enami, T.; Hashimoto, M.; Sato, T.; Onoye, T.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349235.pdf?isnumber=4349216
Power integrity is a crucial design issue for nano-meter technologies
because of decreased supply voltage and increased current. We focused on
gate delay variation caused by power/ground noise, and developed a
full-chip simulation current model with capacitance and a variable
resistor to accurately model current dependency on voltage drop.
Measurement results for 90-nm technology are well reproduced in
simulation. The error of average supply voltage is 0.9% in average.
Measurement results also demonstrate that gate delay depends on average
voltage drop.
-------
CAVLC Encoder Design for Real-Time Mobile Video Applications
Rahman, C. A.; Badawy, W.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349237.pdf?isnumber=4349216
This brief presents a new context-based adaptive variable length coding
(CAVLC) architecture. The prototype is designed for the H.264/AVC
baseline profile entropy coder. The proposed design offers area savings
by reducing the size of the statistic buffer. The arithmetic table
elimination technique further reduces the area. The split VLC tables
simplify the process of bit-stream generation and also help in reducing
some area. The proposed architecture is implemented on Xilinx Virtex II
field-programmable gate array (2v3000fg676-4). Simulation result shows
that the architecture is capable of processing common/quarter-common
intermediate format frame sequences in real-time at a core speed of 50
MHz with 6.85-K logic gates.
-------
******************************
Signal Processing
******************************
LMI Approach to Stability of Direct Form Digital Filters Utilizing
Single Saturation Overflow Nonlinearity
Singh, V.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349239.pdf?isnumber=4349216
A criterion for the elimination of limit cycles in direct form digital
filters utilizing single saturation overflow nonlinearity is presented.
The criterion takes the form of linear matrix inequality and, hence, is
computationally tractable. An example showing the effectiveness of the
present criterion is given.
-------
********************************
Nonlinear Circuits and Systems
********************************
Discrete Lyapunov Exponent and Resistance to Differential Cryptanalysis
Amigo, J. M.; Kocarev, L.; Szczepanski, J.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349217.pdf?isnumber=4349216
In a recent paper, Jakimoski and Subbalakshmi provided a nice connection
between the so-called discrete Lyapunov exponent of a permutation $F$
defined on a finite lattice and its maximal differential probability, a
parameter that measures the complexity of a differential cryptanalysis
attack on the substitution defined by $F$. In this brief, we take a
second look at their result to find some practical shortcomings. We also
discuss more general aspects.
-------
Frequency-Shift Induced by Colored Noise in Nonlinear Oscillators
Maffezzoni, P.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349231.pdf?isnumber=4349216
This brief employs a perturbation phase-domain model to numerically
investigate the phenomenon of frequency-shift induced by colored-noise
in nonlinear oscillators. It is shown that colored-noise with frequency
decaying spectrum tends to induce a frequency-shift phenomenon both in
almost-linear oscillators and in nonlinear topologies such as ring
oscillators. It is also shown that the relevance of the phenomenon
depends linearly on the noise variance.
-------
*************************************
Control Theory and Systems
*************************************
Stochastic Stability of Genetic Networks With Disturbance Attenuation
Li, C.; Chen, L.; Aihara, K.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349229.pdf?isnumber=4349216
Gene regulation is an intrinsically noisy process, which is subject to
intracellular and extracellular noise perturbations and environment
fluctuations. In this brief, we consider a stochastic nonlinear model
for genetic regulatory networks with SUM regulatory functions. Based on
the Lyapunov method and the Lur'e system approach, sufficient conditions
for the stochastic stability of the genetic networks with disturbance
attenuation are derived. The case with time delays owing to the slow
processes of transcription, translation, and translocation is also
studied. All the results are presented in terms of linear matrix
inequalities (LMIs).
------
A Censored Sample Mean Approach to Nonparametric Identification of
Nonlinearities in Wiener Systems
Mzyk, G.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349233.pdf?isnumber=4349216
A new, censored sample mean nonparametric identification algorithm for
estimation of a nonlinear characteristic in Wiener system using properly
preselected input-output data is proposed. Conditions imposed on the
unknown characteristic are weak. In particular, its invertibility and
global continuity are not required. The algorithm is based on
computation of local sample-mean of proper output measurements. The mean
square consistency of the estimate is proved for each continuity point
of the unknown characteristic and the issue of the asymptotic
convergence rate is discussed. Computer simulations are included to
illustrate efficiency of the method also for small and moderate number
of data.
------
****************************************
Circuits and Systems for Communications
****************************************
Feedforward Interference Cancellation in Radio Receiver Front-Ends
Ayazian, S.; Gharpurey, R.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349218.pdf?isnumber=4349216
An interference cancellation technique is described for improving the
dynamic range of receivers. A feedforward approach is used to attenuate
large interferers before the down- conversion mixer in a receiver. This
is accomplished with no measurable impact on the in-band noise
performance. Techniques to cancel interference within a narrowband and
also in multiple bands are described. Simulation results and
measurements from a discrete prototype system are used to validate the
approach.
------
A Quadrature Modulation Transmitter Using Two Frequency Synthesizers
Lee, J.; Cho, S.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349227.pdf?isnumber=4349216
This brief analyzes a novel quadrature modulation transmitter
architecture. The proposed architecture consists of only two frequency
synthesizers, thereby reducing the RF and analog components such as RF
mixer, analog filter, and digital-to-analog converter. Simulation
results show that the bit-error rate and the spectral efficiency of the
proposed method are close to those of conventional quadrature modulation
scheme. The quadrature modulation transmitter can be implemented fully
digitally through the proposed architecture if the all-digital frequency
synthesizer is used.
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Power Systems and Electronic Circuits
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A Wireless Power Interface for Rechargeable Battery Operated Medical
Implants
Li, P.; Bashirullah, R.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349228.pdf?isnumber=4349216
This brief presents a highly integrated wirelessly powered battery
charging circuit for miniature lithium (Li)-ion rechargeable batteries
used in medical implant applications. An inductive link and integrated
Schottky barrier rectifying diodes are used to extract the dc signal
from a power carrier while providing low forward voltage drop for
improved efficiency. The battery charger employs a new control loop that
relaxes comparator resolution requirements, provides simultaneous
operation of constant-current and constant-voltage loops, and eliminates
the external current sense resistor from the charging path. The accuracy
of the end-of-charge (EOC) detection is primarily determined by the
voltage drop across matched resistors and current-sources and the offset
voltage of the sense comparator. Experimental results in 0.6- $mu{hbox
{m}}$ 3M-2P CMOS technology indicate that $pm 1.3%$ (or $pm {20}mu{hbox
{A}}$) EOC accuracy can be obtained under worst case conditions for a
comparator offset voltage of $pm 5~{hbox {mV} }$. The circuit measures
roughly 1.74 ${hbox {mm}}^{2}$ and dissipates 8.4 mW in the charging
phase while delivering a load current of 1.5 mA at 4.1 V (or 6.15 mW)
for an efficiency of 73%.
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Analysis and Implementation of a ZVS-PWM Converter With Series-Connected
Transformers
Lin, B.-R.; Chiang, H.-K.; Chen, C.-C.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349230.pdf?isnumber=4349216
This brief presents the analysis, design, and implementation of
zero-voltage switching (ZVS) active clamp converter with
series-connected transformer. A family of isolated ZVS active clamp
converters is introduced. The technique of the adopted ZVS commutation
will not increase additional voltage stress of switching devices. In the
adopted converter with series-connected transformer, each transformer
can be operated as an inductor or a transformer. Therefore, no output
inductor is needed. To reduce the voltage stress of the switching device
in the conventional forward converter, the active clamp technique is
used to recycle the energy stored in the transformer leakage back into
the input dc source. Finally, experimental results are presented taken
from a laboratory prototype with 100-W rated power, input voltage of 155
V, output voltage of 5 V, and operating at 150 kHz.
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A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier
Oh, W.; Bakkaloglu, B.
http://ieeexplore.ieee.org/iel5/8920/4349216/04349236.pdf?isnumber=4349216
Current feedback amplifiers (CFAs) provide fast response and high slew
rate with Class-AB operation. Fast response, low-dropout regulators
(LDRs) are critical for supply regulation of deep-submicron analog
baseband and RF system-on-chip designs. An LDR with an CFA-based second
stage driving the regulation field-effect transistor is presented. The
low dropout (LDO) achieves an output noise spectral density of 67.7
${hbox {nV}}/sqrt{hbox {Hz}}$, and PSR of 38 dB, both at 100 kHz. In
comparison to an equivalent power consumption voltage feedback buffer
LDO, the proposed CFA-based LDO settles 60% faster, achieving 0.6-$mu
hbox {s} $ settling time for a 25-mA load step. The LDO with CFA buffer
is designed and fabricated on a 0.25-$mu{hbox {m}}$ CMOS process with
five layers of metal, occupying 0.23- ${hbox {mm}}^{2}$ silicon area.
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